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? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? device highlights low power programmable logic ? as low as 2.2 a ? 0.18 m, six layer metal cmos process ? 1.8 v core voltage, 1.8/2.5/3.3 v drive capable i/os ? up to 221 kilobits of sram ? up to 292 i/os available ? up to one million system gates ? nonvolatile, instant-on ? ieee 1149.1 boundary scan testing compliant embedded dual-port sram ? up to twelve dual-port 4-kilobit high performance sram blocks (ql1p075, ql1p100, ql1p200, and ql1p300 devices) ? up to twenty-four dual-port 8-kilobit high performance sram blocks (ql1p600 and ql1p1000 devices) ? embedded synchronous/asynchronous fifo controller ? configurable and cascadable aspect ratio programmable i/o ? bank programmable drive strength ? bank programmable slew rate control ? independent i/o banks capable of supporting multiple i/o standards in one device ? native support for ddr i/os ? bank programmable i/o standards: lvttl, lvcmos, and lvcmos18 advanced clock network ? multiple low skew clock networks 1 dedicated global clock network 4 programmable global clock networks ? quadrant-based segmentable clock networks 20 quad clock networks per device 4 quad clock networks per quadrant 1 dedicated clock network per quadrant ? two user configurable clock managers (ccms) very low power (vlp) mode ? quicklogic polarpro has a special vlp pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device by placing the device in standby. ? enter vlp mode from normal operation in less than 250 s (typical) ? exit from vlp mode to normal operation in less than 250 s (typical) security links there are several security links to disable jtag access to the device. programming these optional links completely disables ac cess to the device from the outside world and provides an extra level of design security not possib le in sram-based fpgas. figure 1: quicklogic polarpro block diagram embedded ram blocks fabric embedded ram blocks fifo controller ccm ddr/gpio gpio gpio gpio gpio gpio gpio gpio gpio gpio ddr/gpio ddr/gpio ddr/gpio ccm fifo controller gpio gpio gpio combining low power, perform ance, density, and embedded ram quicklogic polarpro? data sheet
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 2 ultra-low power fpga combining performance, density, and embedded ram process data quicklogic polarpro is fabricated on a 0.18 , six layer metal cmos process. the core voltage is 1.8 v. the i/o voltage input tolerance and output driv e can be set as 1.8 v, 2.5 v, and 3.3 v. table 1: polarpro product family members features ql1p075 ql1p100 ql1p200 ql1p300 ql1p600 ql1p1000 max gates 75,000 100,000 200,000 300,000 600,000 1,000,000 logic cells 512 640 1,536 1,920 4,224 7,680 max i/o 172 188 292 302 508 652 ram modules 8 8 12 12 24 24 fifo controllers 8 8 12 12 24 24 ram bits 36,864 36,864 55,296 55,296 221,184 221,184 ccms 2 a a. the polarpro 144-pin tqfp and 132-pi n tfbga devices have one ccm. the polarp ro 196-pin tfbga, 256-pin lbga and 324- pin lbga devices have two ccms. 2 a 2222 packages tfbga (0.5 mm) 132 132 132 132 - - tqfp (0.5 mm) 144 144 - - - - tfbga (0.8 mm) 196 196 - - - - lbga (1.0 mm) 256 256 256, 324 256, 324 256, 324 256, 324 table 2: maximum usable i/os device 132 tfbga (8 mm x 8 mm) 144 tqfp 196 tfbga (12 mm x 12 mm) 256 lbga 324 lbga ql1p075 77 97 136 168 - ql1p100 77 97 136 184 - ql1p200 74 - - 184 238 a a. preliminary. ql1p300 74 - - 184 238 a ql1p600 - - - 184 a 238 a ql1p1000 - - - 184 a 238 a
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 3 programmable logic architectural overview the quicklogic polarpro logic cell structure presented in figure 2 is a single register, multiplexer-based logic cell. it is designed for wide fan-in and multiple, simultaneous output functi ons. the cell has a high fan-in, fits a wide range of functions with up to 24 simultaneous in puts (including register control lines), and four outputs (three combinatorial and one registered). the high logi c capacity and fan-in of the logic cell accommodates many user functions with a si ngle level of logic delay. the quicklogic polarpro logic cell can implement: ? two independent 3-input functions ? any 4-input function ? 8 to 1 mux function ? independent 2 to 1 mux function ? single dedicated register with clock en able, active high set and reset signals ? direct input selection to the register, which allows co mbinatorial and register logic to be used separately ? combinatorial logic that can also be configur ed as an edge-triggered master-slave d flip-flop figure 2: polarpro logic cell 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 d e q r s tz cz qz fz qds qst tbs tab tsl ti ta1 ta2 tb1 tb2 bab bsl bi ba1 ba2 bb1 bb2 fs f1 f2 qdi qen qck qrt
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 4 ram modules the polarpro family of devices include two differe nt ram block sizes. the ql1p075, ql1p100, ql1p200, and ql1p300 have 4-kilobit (4,608 bits) ram bloc ks, while the ql1p600 an d ql1p1000 devices have 8-kilobit (9,216 bits) ram blocks. the ram features include: ? independently configurable read and write data bus widths ? independent read and write clocks ? horizontal and vertical concatenation ? write byte enables ? selectable pipelined or non-pipelined read data figure 3: 4-kilobit dual-port ram block a. x=8 for 4-kilobit ram blocks , x=9 for 8-kilobit ram blocks. table 3: ram interface signals signal name function inputs wd [17:0] write data wa [x:0] a a. x=8 for 4-kilobit ram blocks, x=9 for 8-kilobit ram blocks. write address wen [1:0] write enable (two 9-bit enables) wd_sel write chip select wclk write clock ra [x:0] a read address rd_sel read chip select rclk read clock output rd [17:0] read data rd[17:0] wd[17:0] wa[x:0] wen[1:0] wd_sel wclk ra[x:0] rd_sel rclk a a
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 5 the read and write data buses of a ram block can be a rranged to variable bus widths. the bus widths can be configured using the ram wizard avai lable in quickworks, quicklogic?s development software. the selection of the ram depth and width determin es how the data is addressed. the ram blocks also support data concatenation. desi gners can cascade multiple ram modules to increase the depth or width by connecting co rresponding address lines together and dividing the words between modules. generally, this requires the use of additi onal programmable logic resources. however, when concatenating only two 4-kilobit ram blocks or two 8-kilobit ram blocks, they can be concatenated horizontally or vertically without using any additional programmable fabric resources. for example, two internal 4-kilobit dual-port ram bloc ks concatenated vertically to create a 512x18 ram block or horizontally to create a 256x36 ram block. a bl ock diagram of horizontal an d vertical concatenation is displayed in figure 4 . figure 4: horizontal and vertical concatenation examples table 4 shows the various ram configurations su pported by the polarpro ram modules. table 4: available dual-port ram configurations device number of ram blocks depth width ql1p075 ql1p100 ql1p200 ql1p300 1 256 1-18 1 512 1-9 2 256 1-36 2 512 1-18 2 1024 1-9 ql1p600 ql1p1000 1 512 1-18 1 1024 1-9 2 512 1-36 2 1024 1-18 2 2048 1-9 256x36 dual-port ram rd[35:0] horizontal concatenation 512x18 dual-port ram vertical concatenation wd[35:0] wa[7:0] wen[3:0] wd_sel wclk ra[7:0] rd_sel rclk wd[17:0] wa[8:0] wen[1:0] wd_sel wclk ra[8:0] rd_sel rclk rd[17:0]
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 6 true dual-port ram polarpro dual-port ram modules can also be concatenat ed to generate true dual -port rams. the true dual- port ram module?s port1 and port2 have completely independent read and write ports, and separate read and write clocks. this allows port1 and port2 to have di fferent data widths and clock domains. it is important to note that there is no circuitry preventing a write an d read operation to the same address space at the same time. therefore, it is up to the designer to ensure that the same address is not read from and written to simultaneously, otherwise the data is considered invali d. likewise, the same address must not be written to from both ports at the same time. however, it is possible to read from the same address. figure 5 shows an example of a 512x18 true dual-port ram. figure 5: 512x18 true dual-port ram block table 5: true dual-port ram interface signals port signal name function port1 inputs port1_wd[17:0] write data port1_a[8:0] write address port1_wen[1:0] write enable port1_cs chip select port1_clk clock output port1_rd[17:0] read data port2 inputs port2_wd[17:0] write data port2_a[8:0] write address port2_wen[1:0] write enable port2_cs chip select port2_clk clock output port2_rd[17:0] read data port2_rd[17:0] port1_wd[17:0] port1_a[8:0] port1_wen port1_cs port1_clk port2_wd[17:0] port2_a[8:0] port2_wen port2_cs port2_clk port1_rd[17:0]
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 7 embedded fifo controllers every ram block can be implemented as a synchronou s or asynchronous fifo. there are built-in fifo controllers that allow for varying depths and widths without requiring programmable fabric resources. the polarpro fifo controller features include: ? x9, x18 and x36 data bus widths ? independent push and pop clocks ? independent programmable data width on push and pop sides ? configurable synchronous or asynchronous fifo operation ? 4-bit push and pop level indicators to provide fifo status outputs for each port ? pipelined read data to improve timing figure 6: fifo module table 6: available true dual-port ram configurations device depth width ql1p075 ql1p100 ql1p200 ql1p300 512 1-18 1024 1-9 ql1p600 ql1p1000 512 1-36 1024 1-18 2048 1-9 din[x:0] push fifo_push_flush push_clk pop fifo_pop_flush pop_clk dout[x:0] almost_full almost_empty push_flag[3:0] pop_flag[3:0] a a a. x = {1,2,3,....35}.
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 8 table 8 lists the fifo controller interface signals. table 7: available fifo configurations device number of ram blocks depth supported widths ql1p075 ql1p100 ql1p200 ql1p300 1 256 1-18 bits 1 512 1-9 bits 2 256 1-36 bits 2 512 1-18 bits 2 1024 1-9 bits ql1p600 ql1p1000 1 512 1-18 bits 1 1024 1-9 bits 2 512 1-36 bits 2 1024 1-18 bits 2 2048 1-9 bits table 8: fifo interface signals signal name width (bits) direction function push signals din 1 to 36 i data bus input push 1 i initiates a data push fifo_push_flush 1 i empties the fifo push_clk 1 i push data clock pop signals dout 1 to 36 o data bus output pop 1 i initiates a data pop fifo_pop_flush 1 i empties the fifo pop_clk 1 i pop data clock status flags almost_full 1 o asserted when fifo has one location available almost_empty 1 o asserted when fifo has one location used push_flag[3:0] 4 o fifo push level indicator pop_flag[3:0] 4 o fifo pop level indicator
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 9 table 9 and table 10 highlight the corresponding fifo level indi cator for each 4-bit value of the push_flag and pop_flag outputs. table 9: fifo push level indicator values value status 0000 full 0001 empty 0010 room for more than one-half 0011 room for more than one-forth 1000 room for 8 or more 1001 room for 7 1010 room for 6 1011 room for 5 1100 room for 4 1101 room for 3 1110 room for 2 1111 room for 1 others reserved table 10: fifo pop level interface signals value status 0000 empty 0001 1 entry in fifo 0010 2 entries in fifo 0011 3 entries in fifo 1000 4 entries in fifo 1010 5 entries in fifo 1100 6 entries in fifo 1110 7 entries in fifo 1000 8 or more entries in fifo 1101 one-forth or more full 1110 one-half or more full 1111 full others reserved
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 10 fifo flush procedure both push and pop domains are provided with a flush in put signal synchronized to their respective clocks. when a flush is triggered from one si de of the fifo, the sign al propagates and re-synchronizes internally to the other clock domain. during a flush operation, the valu es of the fifo flags are invalid for a specific number of cycles (see figure 7 and figure 8 ). as shown in figure 7 , when the fifo_push_flush asserts, the almost_full and push_flag signals become invalid until the fifo can flush the data with re gards to the push clock domain as well as the pop clock domain. after the fifo_push_flush is asserted, the next rising edge of the pop clock starts the pop flush routine. figure 7 illustrates a fifo flush operation. after the fifo_push_flush is asserted at 2 ( push_clk ), four pop clock cycles (12 through 15) are required to update the pop_flag , and push_flag signals. the almost_empty signal is asserted to indicate that the pu sh flush operation has been completed. on the following rising edge of the push_clk (8), the push_flag is accordingly updated to reflect the successful flush operation. figure 7: fifo flush from push side figure 8 illustrates a pop flush operation. after the fifo_pop_flush is asserted at 2 ( pop_clk ), four push clock cycles (12 through 15) are required to update the pop_flag , and push_flag signals. the almost_empty signal is asserted to indicate that the po p flush operation has been completed. on the following rising edge of the pop_clk (8), the pop_flag is updated accordingly to reflect the successful flush operation. push_clk fifo_push_flush pop_clk almost_full push_flag valid almost_empty pop_flag 0000 (empty) earliest push valid valid 12 3456 8 7910 11 12 13 14 15 16 invalid invalid invalid
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 11 figure 8: fifo flush from pop side figure 7 and figure 8 are only true for this particular push-p op clock frequency combination. the clock frequency and phase difference between pop_clk and pu sh_clk can cause an additional flush delay of one clock cycle in either domain because of the as ynchronous relationship between the two clocks. distributed clock networks global clocks the polarpro clock network architecture cons ists of a 2-level h-tree network as shown in figure 9 . the first level of each clock tree (high-lighted in red) spans from the clock input pad to the global clock network and to the center of each quadrant of the chip. the second le vel (high-lighted in blue) sp ans from the quadrant clock network to every logic cell inside that quadrant. there ar e five global clocks in th e global clock network, and five quadrant clocks in each quadrant clock network. all global clocks drive the quadrant clock network inputs. the quadrant clocks output to clock in version muxes, which pass either the original input clock or an inverted version of the input clock to the logic cells in that quadrant. the clock networks can drive ram block clock inputs and reset, set, enable, and cloc k inputs to i/o registers. furtherm ore, the quadrant clock outputs can be routed to all logic cell inputs. pop_clk fifo_pop_flush push_clk almost_empty pop_flag 0000 (empty) almost_full push_flag valid invalid valid valid earliest push invalid 1 10 23456789 11 12 13 14 15 16 invalid
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 12 figure 9: global clock architecture of the five global clock networks, four can be either driven directly by clock pads, configurable clock manager (ccm) outputs, or internally generated signals. these four clock nets go through 3-input global clock muxes located in the middle of the die. see figure 10 for a diagram of a 3-input glob al clock mux. the fifth is a dedicated global clock networ k that goes directly to the quadrant qu ad-net clock network and is used as a dedicated fast clock. figure 10: global clock structure quadrant clock network global clock network x4 x4 x4 x4 x4 inversion mux quadrant clock network quadrant clock network quadrant clock network inte r na l ly ge ne ra te d c loc k , or clock from general routing network global clock (clk ) input pad t o quadrant c loc k s tructure g loba l c loc k b uffer ccm output 2-bit select
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 13 figure 11 illustrates the quadrant clock 2-input mux. figure 11: quadrant clock structure it is important to note that the select lines for the glob al clock and quad-net muxes are static signals and cannot be changed dynamically during device operation. fo r more information about global and quad-net clock networks and how to use them, refer to application note 85 clock networks in polarpro devices at http://www.quicklogic.com /images/appnote85.pdf . dynamic clock enable devices in the quicklogic polarpro family, ql1p200 and larger, provide a powerful dynamic clock enable feature that allows designers to dynamically enable an d disable clocks routed into the quicklogic device. associated with each of the five cloc k inputs is a clock enable, which is an interface signal that can be either dynamically controlled via a routable signal or tied high or low. once an incoming clock is disabled, the clock is driven low internally. all the logic that is driven by the clock is held at the state when the clock was disabled. if a reset signal is passed through the clock pad, the dynamic disable should not be used. as an additional feature, polarpro devices have built-i n deglitching circuitry to prevent clock glitching during transitions so that clocks can be enabled or disabled asynchronously without the possibility of false edge detection within the internal logic. the dynamic clock disable feature can be implemented in verilog, vhdl, and schematic designs by instantiating the dynamic clock enable macro, clock2_dyn_en. figure 12 , shows the schematic representation of the dynamic clock enable macro. figure 12: clock pad macro for dynamic clock enable inte r na l ly ge ne ra te d c loc k , or clock from general routing network t o invers ion mux, then logic cells logic cell q ua dra nt c loc k b uffer f rom g lobal clock buffer 1-bit select
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 14 configurable clock managers the ccm features include: ? input frequency range from 25 mhz to 200 mhz ? output frequency range from 25 mhz to 200 mhz ? output jitter is less than 200 ps peak-to-peak ? two outputs: pullout0 (with 0 ph ase shift), and pullout1 (with an op tion of 0, 90, 180, or 270 phase shift plus a programmable delay). ? programmable delay allows delays up to 2.5 ns at 250 ps intervals ? fixed feedback path ? output frequency lock time in less than 10 s figure 13: configurable clock manager the reset signal can be routed from a clock pad or gene rated using internal logic. the lock_out signal can be routed to internal logic and/or an output pad. both ccm clock outputs can drive the global clock networks, as well as any general purpose i/o pin. once the ccm has synchronized the output clock to the incoming clock, the lock_out signal will be asserted to indicate that the output clock is valid. lock detection requires at least 10 s after reset to assert lock_out. the polarp ro ccms have three modes of operation, based on the input frequency and desired output frequency. table 11 indicates the features of each mode. table 11: ccm pll mode frequencies output frequency input frequency range output frequency range pll mode x1 25 mhz to 200 mhz 25 mhz to 200 mhz pll_mult1 x2 25 mhz to 100 mhz 50 mhz to 200 mhz pll_mult2 x4 25 mhz to 50 mhz 100 mhz to 200 mhz pll_mult4 pllout0 ded_in ded_fd rst_in fc[1:0] s[1:0] tdctl[3:0] pllout1 lock_out
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 15 ccm signals table 12 provides the name, direction, functi on and description of the ccm ports. table 13 , table 14 , and table 15 give the values used to configure the set mode, phase shift control and time delay control bits. table 12: ccm signals signal name direction function description routable ports ded_in i dedicated input clock pad ccm input source. ded_fd i dedicated feedback automatically calculated and routed by the software tools. rst_in i reset active high reset: if rst_in is asserted, pllout0 and pllout1 are reset to 0. this signal must be asserted and then released for lock_out to assert. pllout0 o 0 phase clock 0 phase clock output. pllout1 o configurable phase clock 0, 90,180, or 270 phase clock output with programmable delay. lock_out o lock detect active high lock detection signal. active when the pllout signals correctly output t he configured functionality. static ports fc[1:0] i phase shift control determines whether pllout1 is 0, 90, 180, or 270 degrees out of phase with pllout0 a . a. the pllout1 output can vary up to -5% with respect to t he pllout0 output. therefore, quicklogic recommends thorough post-lay out simulation in order to verify satisfactory operation of the ccms. s[1:0] i set mode determines pllout1 and pllout0 frequency multiplier (x1, x2, or x4). tdctl[3:0] i time delay control pllout1 programmable delay, configurable in 250 ps increments up to a maximum of 2.5 ns. note: 250 ps can vary depending on process variation. table 13: set mode values s[1:0] multiplier 00 x1 01 x2 10 x4 11 reserved table 14: phase shift control values fc[1:0] phase shift (deg.) 00 0 01 90 10 180 11 270
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 16 ccm configurations the main purpose of the ccm is to align the clock arri val times of two separate clock destinations, whether it is within the fpga or external to the chip. the diffe rence between the two clock destinations is referred to as clock skew. to correct for clock skew the ccms can be configured to shift the phase and/or delay of the pllout1 clock output. in most cases the desired phase or added delay can be ac complished by configuring bo th the clock source input and feedback input as dedicated. in the case of a dedicated clock source and dedicated feedback, the quicklogic development software calcul ates and generates all of the requir ed routing delays to produce the requested configuration. for more information on ccms and how to use them in quickworks, refer to application note 87 configurable clock managers at http://www.quicklogic.com /images/appnote87.pdf . table 15: time delay control values tdctl[3:0] time delay (ps) 0000 0 0001 250 0010 500 0011 750 0100 1000 0101 1250 0110 1500 0111 1750 1000 2000 1001 2250 1010 2500 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 16: available configurations clock feedback example usage comments dedicated clock pad dedicated feedback standard pll application. reduce set-up or clock-to-out time. if the clock pad and destination are in phase.
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 17 simultaneously switching out puts (ssos) while using a ccm ssos are outputs that transition at the same time in the same direction (either from vcc to gnd or gnd to vcc). to ensure that the ccms never lose lock over all possible frequencies of operation, designers must follow the guidelines specified in th is section when using the fpga output s as ssos. these guidelines include the number of ssos placed adjacent to the ccms and the quality of the power filtering circuit sourcing the ccm block. figure 14 shows a basic layout of the four i/o banks (ban k a, bank b, bank c and bank d) available in polarpro devices and the relative placem ent of the two ccms (ccm<0> and ccm<1>). figure 14: basic layout of i/o banks and ccms ssos placed in bank c and bank d in close proxim ity to ccm<0> may affect that ccm?s functionality. similarly, ssos placed in bank a and bank d in close proximity to ccm<1> may affect that ccm?s functionality. note: to define the boundary of operation when using ssos in conjunction with ccms, add ssos starting from the far end of a bank relative to the ccms location. for example, when using ccm<1>, add ssos in bank a starting from the far bottom right and in bank d starting from the far top left (see figure 15 ). the same applies for ccm<0> in reverse positioning. ccm<1> bank b bank c bank a bank d ccm<0>
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 18 figure 15: adding ssos when using ccm<1> to ensure proper operation of the ccm(s) use the following guidelines: 1. limit the number of ssos in bank a and bank d that are synchronous to ccm<1> (i.e., clocked by ccm<1> outputs) and ssos in bank c and bank d th at are synchronous to ccm<0> (i.e., clocked by ccm<0> outputs) as shown in table 17 , table 18 , and table 19 . note: for example, refer to row 7 highlighted in table 17 . if 56 ssos are placed with a slew rate setting of wow, up to 24 ssos can be placed in bank a (ccm<1>) or bank c (ccm<0>) and up to 48 ssos can be placed in bank d. similarly, with a slew rate setting of slow, up to 36 ssos can be placed in bank a (ccm<1>) or bank c (ccm<0>) and up to 48 ssos can be placed in bank d. however, if 60 ssos are placed on bank a (ccm<1>) or bank b (ccm<0>), a slew rate setting of wow cannot be used, but slew rate settings such as very fast, fast and slow can be used. ccm<1> bank b bank c bank a bank d ccm<0>
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 19 table 17: usable synchronous ssos at vccio = 3.3 v total sso in (bank a and bank d) or (bank c and bank d) slew rate setting wow very fast fast slow max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d ql1p075 and ql1p100 8 88888888 16 16 16 16 16 16 16 16 16 24 24 24 24 24 24 24 24 24 32 24 32 32 32 32 32 32 32 40 24 40 36 40 36 40 36 40 48 24 48 36 48 36 48 36 48 56 24 48 36 48 36 48 36 48 60 36 40 36 48 36 48 64 36 40 36 48 36 48 72 36 48 36 48 76 36 40 36 48 84 36 48 ql1p200 and ql1p300 8 88888888 16 16 16 16 16 16 16 24 24 24 24 24 24 16 32 24 32 32 32 32 16 40 24 40 36 32 36 16 48 24 40 36 32 36 16 56 60 64 72 76 84
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 20 table 18: usable synchronous ssos at vccio = 2.5 v total sso in (bank a and bank d) or (bank c and bank d) slew rate setting wow very fast fast slow max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d ql1p075 and ql1p100 8 88888888 16 16 16 16 16 16 16 16 16 24 24 24 24 24 24 24 24 24 32 32 32 32 32 32 32 32 32 40 36 40 36 40 36 40 36 40 48 36 48 36 48 36 48 36 48 56 36 48 36 48 36 48 36 48 60 36 48 36 48 36 48 36 48 64 36 48 36 48 36 48 36 48 72 36 48 36 48 36 48 36 48 76 36 48 36 48 36 48 84 36 48 36 48 36 48 ql1p200 and ql1p300 8 88888888 16 16 16 16 16 16 16 16 16 24 0 24 24 24 24 24 24 24 32 32 24 32 24 32 32 40 36 24 36 24 36 40 48 36 24 36 24 36 48 56 36 24 36 24 36 48 60 36 24 36 24 36 48 64 36 48 72 36 48 76 36 40 84
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 21 table 19: usable synchronous ssos at vccio = 1.8 v total sso in (bank a and bank d) or (bank c and bank d) slew rate setting wow very fast fast slow max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d ql1p075 and ql1p100 8 8888n/an/an/an/a 16 16 16 16 16 n/a n/a n/a n/a 24 24 24 24 24 n/a n/a n/a n/a 32 32 32 32 32 n/a n/a n/a n/a 40 36 40 36 40 n/a n/a n/a n/a 48 36 48 36 48 n/a n/a n/a n/a 56 36 48 36 48 n/a n/a n/a n/a 60 36 48 36 48 n/a n/a n/a n/a 64 36 48 36 48 n/a n/a n/a n/a 72 36 48 36 48 n/a n/a n/a n/a 76 36 48 36 48 n/a n/a n/a n/a 84 36 48 36 48 n/a n/a n/a n/a ql1p200 and ql1p300 8 8888n/an/an/an/a 16 16 16 16 16 n/a n/a n/a n/a 24 24 24 24 24 n/a n/a n/a n/a 32 32 32 32 32 n/a n/a n/a n/a 40 36 40 36 32 n/a n/a n/a n/a 48 36 48 36 32 n/a n/a n/a n/a 56 36 48 36 32 n/a n/a n/a n/a 60 36 48 36 32 n/a n/a n/a n/a 64 24 48 32 32 n/a n/a n/a n/a 72 n/a n/a n/a n/a 76 n/a n/a n/a n/a 84 n/a n/a n/a n/a
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 22 2. limit the number of ssos in bank a and bank d that are asynchronous to ccm<1> (i.e., not clocked by ccm<1> outputs) and ssos in bank c and bank d th at are asynchronous to ccm<0> (i.e., not clocked by ccm<0> outputs) as shown in table 20 , table 21 , and table 22 . table 20: usable asynchronous ssos at vccio = 3.3v total sso in (bank a and bank d) or (bank c and bank d) slew rate setting wow very fast fast slow max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d ql1p075 and ql1p100 8 88888888 16 16 16 16 16 24 24 24 24 24 32 32 24 32 24 40 36 24 36 24 48 36 24 36 24 56 36 24 60 36 24 ql1p200 and ql1p300 8 80888888 16 16 16 16 16 16 8 24 16 8 242424 8 32 32 24 32 8 40 36 24 36 8 48 56 60
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 23 table 21: usable asynchronous ssos at vccio = 2.5 v total sso in (bank a and bank d) or (bank c and bank d) slew rate setting wow very fast fast slow max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d ql1p075 and ql1p100 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 24 16 24 24 24 24 24 24 24 32 32 32 32 32 32 32 40 36 32 36 32 36 40 44 36 32 36 32 36 40 48 36 32 36 32 36 40 56 32 32 36 32 36 40 60 36 24 36 40 64 36 40 68 36 32 ql1p200 and ql1p300 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 24 24 24 24 24 24 16 32 32 24 32 32 32 16 40 36 24 36 32 36 16 44 36 24 36 32 36 16 48 32 24 36 32 36 16 56 60 64 68
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 24 3. the power supply to the ccms must ha ve adequate noise filtering circui ts. quicklogic reference design boards use the noise filtering circuit shown in figure 16 . figure 16: noise filtering circuit table 22: usable asynchronous ssos at vccio = 1.8 v total sso in (bank a and bank d) or (bank c and bank d) slew rate setting wow very fast fast slow max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d max. sso in bank a/ bank c max. sso in bank d ql1p075 and ql1p100 8 8 8 8 8 n/a n/a n/a n/a 16 16 16 16 16 n/a n/a n/a n/a 24 24 24 24 24 n/a n/a n/a n/a 32 32 32 32 32 n/a n/a n/a n/a 40 32 40 36 40 n/a n/a n/a n/a 44 16 40 36 40 n/a n/a n/a n/a 48 16 40 36 40 n/a n/a n/a n/a 56 16 40 36 40 n/a n/a n/a n/a 60 36 40 n/a n/a n/a n/a 64 24 40 n/a n/a n/a n/a 68 n/a n/a n/a n/a ql1p200 and ql1p300 8 8 8 8 8 n/a n/a n/a n/a 16 16 8 16 16 n/a n/a n/a n/a 24 16 8 24 24 n/a n/a n/a n/a 32 32 24 n/a n/a n/a n/a 40 36 24 n/a n/a n/a n/a 44 36 24 n/a n/a n/a n/a 48 36 24 n/a n/a n/a n/a 56 36 24 n/a n/a n/a n/a 60 36 24 n/a n/a n/a n/a 64 n/a n/a n/a n/a 68 n/a n/a n/a n/a polarpro 1.8v gnd 0.01uf 0.001uf ccmvcc ccmgnd mi0805k400r-10
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 25 general purpose input output (gpio) cell structure the gpio features include: ? direct or registered input with input path select ? direct or registered output with output path select ? direct or registered output enable with oe path select ? input buffer enable to reduce power ? programmable weak keeper, programmable pull-up/pull-down control ? programmable drive strength ? configurable slew rate ? support for jtag boundary scan figure 17: polarpro gpio cell fixhold logic dq d q dq outz outrz_en osel oez esel inz isel inrz_en fixhold rst clk di_en pbe pbd pbk i/o pad slew[1:0] p[3:0] weak pull-up/pull-down controller slew rate & drive strength logic
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 26 with bi-directional i/o pins and global clock input pins, the polarpro device maximizes i/o performance, functionality, and flexibility. all input and i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply with the specific i/o standard selected. for single-ended i/o standard s, the corresponding vcci o bank input specifies the input tolerance and the output drive voltage. drive strength and slew rate are configured for an entire bank. weak keeper, pull-up, and pull-down functions can be c onfigured for individual i/o. the default configuration for quicklogic quickworks softwar e has the drive strength set to 4 and the slew rate set to wow. table 23: gpio interface signals signal name direction function routable signals outz i data out from internal logic outrz_en i enable for registered outz oez i tristate enable for the output signal inz o input signal to the internal logic inrz_en i enable for registered inz rst i reset for optional registers clk i clock signal for optional registers di_en i enable for i/o input signal. drives a 1 to internal logic when disabled. static signals slew[1:0] i 2-bit slew rate control p[3:0] i programmable drive strength osel i select signal for registered or flow through outz esel i select signal for registered or flow-through oez isel i select signal for registered or flow-through inz fixhold i enable control for i/o input delay for hold fixing pbe i input signals for the weak keeper, pull-up/pull-down controller, see table 24 for functional behavior pbd i pbk i
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 27 programmable weak keeper, pull-up, and pull-down a programmable weak keeper, pull-up or pull-down contro ller is also available on each general purpose i/o bank. when implementing the weak keeper, pull-up, an d pull-down functions, eac h i/o can be configured separately. the i/o weak pull-up and pull-down eliminates the need for external resistors. when pbk=1 the keeper block is placed into keeper mode. in the keeper mode , the pad pin (if the driver is tristated), will be kept at whichever level it was last forced, either by the driver itself, or by an external driver. programmable drive strength every gpio has independent drive strength control. twel ve different drive strength levels are available for designers to choose from. for additional info rmation about corresponding drive strength see dc characteristics on page 35. programmable slew rate each i/o has programmable slew rate capability. the po larpro gpios allow up to four different slew rate speeds (slow, fast, vfast, and wow). sl ower slew rates can be used to redu ce noise caused by i/o switching. i/o interface standards are programmable on a per bank basis. table 25 illustrates the i/o bank configurations available. each i/o bank is independent of other i/o banks and each i/o bank has its own vccio supply inputs. a mixture of diffe rent i/o standards can be used on a polarpro device. however, there is a limitation as to which i/o standards can be supp orted within a given bank. on ly standards that share a common vccio can be shared within the same bank (e.g., pci and lvttl). table 24: weak pull-up, and pull-down controller pbk pbd pbe function 0 0 0 tristate (floating) 0 0 1 weak pull-down 0 1 1 weak pull-up 1 x x weak keeper (retains state) 0 1 0 reserved table 25: i/o standards and applications i/o standard vccio voltage application lvttl 3.3 v general purpose lv c m o s 2 5 2.5 v general purpose lvcmos18 1.8 v general purpose pci 3.3 v pci bus applications
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 28 ddrio cell structure quicklogic polarpro devices support ddrios, which allows clocking data on both the positive and negative clock edges. all polarpro devices have one i/o bank (b ank d) that can be configured in either a gpio bank or a ddrio mode. when bank d is configured to ddrio mode, it is further divided into ddrio sets. each set contains 12 i/os, which include 8 dqs, 1 dqm, 1 dqs, 1 dqck_n and 1 dqck_p (for the differential clocks, refer to table 26 ). figure 18: polarpro ddrio block diagram table 26: available ddr sets polarpro device package number of ddr sets ql1p075 pf144 2 pt196 4 ps256 4 ql1p100 pf144 2 pt196 4 ps256 4 ql1p200 ps256 4 ps324 4 ql1p300 ps256 4 ps324 4 ql1p600 ps256 4 ps324 4 ql1p1000 ps256 4 ps324 4 dq dq dq dq dq dqs dqck_n dqck_p dq dq dq dqm ddr set2 ddr set1
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 29 double data rate (ddr) i/o the ddr features include: ? programmable slew rate ? programmable drive strength ? programmable pull-up figure 19: ddrio dq configuration dqs_shf clk_sync clk dqhi dqli/inz oez ddr_en clk 270 dqh dql/outz osel doi esel dq ddr_en ddr_en ddr_en vref + -
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 30 figure 20: ddrio dqs configuration table 27: ddr dq fabric interface signals signal name direction function routable signals ddr_en i enable ddr function, otherwise function will be that of gpio. clk270 i shifted clock used in center-alig ning data with dqs in writing out data. pdb i used as control for differential power-down. clk i system clock signal from the programmable fabric. rst i reset signal for registers inside the i/o. inrz_en i enable for registered dqli / inz. dqh i higher bit dq signal output from core. outrz_en i gpio: enable for registered outz signal. dql / outz i ddr(dql): lower bit dq signal output from core. gpio(outz): data out from core with optional register. oez i tristate enable for the out put signal with optional register. dqhi o higher bit dq signal input to core with optional register fo r resynchronization. dqli / inz o ddr(dqli): lower bit dq signal input to core with optional register for resynchronization. gpio(inz): data in signal to core with optional register. doi dqs vref + - dqs delay wrt_en/ outz clk osel resynch_wq_wr ddr_en oez isel inz dqs_shf fsel ddr_en resynch_ dq_wr
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 31 static signals resync_dq_rd i signal to enable resynching of dq being read to avoid setup violations inside the programmable fabric. resync_dq_wr i signal to enable resynching of dq being written to avoid setup violations inside the i/o. slew[1:0] i 2-bit slew rate control. p[3:0] i pull-up programmable drive strength. n[3:0] i pull-down programmable drive strength. fixhold i enable control for i/o input delay for hold fixing. pbe i input signal for weak pull-up controller. doi i used as control for data out inversion. isel i select signal for registered or flow through inz. osel i select signal for registered or flow through outz. esel i select signal for regist ered or flow through oez. table 28: ddr dqs interface signals signal name direction function routable signals clk_sync i optional resynchronization cloc k to sync incoming data with the programmable fabric system clock. pdb i control for differential power-down. clk i system clock signal from the programmable fabric. rst i reset signal for registers inside the i/o. inrz_en i gpio: enable for registered inz. inz o gpio: data in signal to core with optional register. dqs_br_rel i a read burst signal used to mask the end of dqs pulses to avoid unnecessary glitches that will result in clocking-in unwanted data. oez i tristate enable for the output signal with optional register. outrz_en i enable for registered or flow-through wrt_en/outz. wrt_en i ddr(wrt_en): write enable signal. gpio(outz): data out from core with optional register. static signals clk_sync_del_ ctrl[4:0] i setting to program delay for clk_sync. clk_sync_inv i option to invert clk_sync. resync_dq_wr i signal to enable resynching of dq being written to avoid setup violations inside i/o. ddr_en i enable ddr function, otherwise f unction will be that of gpio. fixhold i enable control for i/o input delay for hold fixing. table 27: ddr dq fabric interface signals (continued) signal name direction function
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 32 ddrio in gpio mode ddr in gpio mode features include programmable i/o standards via th e vccio input pins (1.8v lvcmos, 2.5v lvcmos, and 3.3v lvttl). note: ddrios do not support pci. for pci support use the general purpose i/os. very low power (vlp) mode the quicklogic polarpro devices have a unique feat ure, referred to as vlp mode, which reduces power consumption by placing the device in standby. specific ally, vlp mode can bring the total standby current down to less than 10 a at room temperature when no incoming signals are toggled. vlp mode is controlled by the vlp pin. the vlp pin is active low, so vlp mode is activated by pulling the vlp pin to ground. conversely, the vlp pin must be pulled to 3.3 v for normal operation. when a polarpro device goes into vlp mode, the following occurs: ? all logic cell registers and gpio registers values are held ? all ram cell data is retained ? the outputs from all gpio to the in ternal logic are tied to a weak ?1? ? gpio outputs drive the previous values ? gpio output enables retain the previous values ? ddrio outputs are pulled down through a weak pull down circuit ? clock pad inputs are gated ? ccms are held in the reset state the entire operation from normal mode to vlp mode requires 250 s (300 s maximum). as mentioned in the vlp behavioral description above, the output of the gpio to the internal logic is a weak ?1? . therefore, to preserve data retention gpio should no t be used for a set, reset, or clock signal. pbe i input signal for weak pull-up controller. slew[1:0] i slew rate control setting. p[3:0] i pull-up programmable drive strength. n[3:0] i pull-down programmable drive strength. doi i control for data out inversion. isel i ddr: selects between vref (isel=0) or padi (isel=1), to connect to the inverting-input of a differential amplifier inside the ddr i/o driver. gpio: select signal for registered or flow-through inz. osel i select signal for registered or flow-through wrt_en/outz. esel i select signal for registered or flow-through dqs_oe/oez. dqs_del_ ctrl[3:0] i setting to program delay of dqs signal. table 28: ddr dqs interface signals (continued) signal name direction function
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 33 as the device exits out of vlp mode, the data from the registers, ram, and gpio will be used to recover the functionality of the device. furthermore, since the ccms we re in a reset state during vlp mode, they will have to re-acquire the correct output signals before assertin g lock_out. the time required to go from vlp mode to normal operation is 250 s (300 s maximum). figure 23 displays the delays asso ciated with entering and exiting vlp mode. figure 21: typical vlp mode timing joint test access group (jtag) information figure 22: jtag block diagram vlp pin vlp status vlp mode normal operation vlp inactive vlp inactive 250us 250us tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 34 quicklogic?s polarpro family comp lies with ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible devi ce through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run three required tests along with several user-defined tests. jtag tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for comprehensiv e verification of higher level system elements. the 1149.1 standard requires the following three tests: ? extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and te st data out (tdo) pins. boundary scan cells are preloaded with test patterns (through the sample/pre load instruction), and input boundary cells capture the input data for analysis. ? sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed thro ugh a data scan operation, allowing users to sample the functional data entering and leaving the device. ? bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass regist er. the bypass instruction allows user s to test a device without passing through other devices. the bypass register is conn ected between the tdi and tdo pins, allowing serial data to be transferred through a device wi thout affecting the operation of the device. jtag bsdl support ? boundary scan description language (bsdl) ? machine-readable data for test equipmen t to generate testing vectors and software ? bsdl files available for all device /package combinations from quicklogic ? extensive industry support available and at vg (automatic test vector generation)
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 35 electrical specifications dc characteristics the dc specifications are provided in table 29 through table 32 . table 29: absolute maximum ratings parameter value parameter value vcc voltage -0.5 v to 2.2 v latch-up immunity 100 ma vccio voltage -0.5 v to 4.0 v esd pad protection 2 kv vref voltage -0.5 v to 2.0 v leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to 4.0 v laminate package (bga) storage temperature -55 c to + 125 c table 30: recommended operating range symbol parameter military industrial commercial unit min. max. min. max. min. max. vcc supply voltage 1.71 1.89 1.71 1.89 1.71 1.89 v vccio i/o input tolerance voltage 1.71 3.60 1.71 3.60 1.71 3.60 v tj junction temperature -55 125 -40 100 0 85 c table 31: dc characteristics symbol parameter conditions min. typ. max. units i l i or i/o input leakage current vi = vccio or gnd - - 1 a i oz 3-state output leakage curr ent vi = vccio or gnd - - 1 a c i i/o input capacitance vccio = 3.6 v - - 10 pf c clock clock input capacitance vccio = 3.6 v - - 10 pf i ref quiescent current on inref - - - 5 a i pd current on programmable pull-down vccio = 3.6 v -200 - -50 a vccio = 2.75 v -150 - -25 a vccio = 1.89 v -100 - -10 a i pu current on programmable pull-up vccio = 3.6 v 50 - 200 a vccio = 2.75 v 25 - 150 a vccio = 1.89 v 10 - 100 a i vlp quiescent current on vlp pin vlp=3.3 - 1 10 a i ccm quiescent current on each ccmvcc vcc=1.89 v - 1 10 a i vcc quiescent current vlp=gnd 2.2 40 a vlp=3.3v - 40 100 a i vccio quiescent current on vccio vccio = 3.6 v - 2 10 a vccio = 2.75 v - 2 10 a vccio = 1.89 v - 2 10 a
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 36 table 33 and table 34 lists the worst case process (t j =125c) output currents (in ma) across the output driver at three levels of i/o voltages. all drive streng th data was measured at i/o voltages of 0.4 v and vccio - 0.4 v. table 32: dc input and output levels a a. the data provided in table 32 represents the jedec and pc i specification. quicklogic devices either meet or exceed these requirements. symbol inref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lv t t l n/a n/a -0.3 0.8 2.2 vccio + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 vccio + 0.3 0.7 1.7 2.0 -2.0 lv c m o s 1 8 n/a n/a -0.3 0.63 1.2 vccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 vccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x vccio 0.6 x v ccio vccio + 0.5 0.1 x vccio 0.9 x vccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 vccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 vccio + 0.3 1.10 1.90 8 -8 table 33: gpio programmable drive strength drive strength ioh (ma) iol (ma) 1.8v 2.5v 3.3v 1.8v 2.5v 3.3v 1 2.2 2.8 3.2 1.7 2.3 2.7 2 4.1 5.2 5.9 3.4 4.4 5 3 6.2 7.8 8.8 5.1 6.7 7.6 4 8 10 11.2 6.6 8.6 9.7 5 10 12.4 13.9 8.3 10.7 12.1 6 11.8 14.6 16.3 9.8 12.7 14.2 7 13.7 16.9 18.9 11.5 14.7 16.6 8 15.3 18.9 21 12.9 16.5 18.5 9 17.1 21.1 23.4 14.5 18.5 20.7 10 18.8 23 25.5 15.9 20.2 22.6 11 20 25 27.6 17.4 22 24.6 12 21.7 26.4 29.1 18.6 23.5 26.1 n/a reserved
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 37 table 34: ddrio programmable drive strength drive strength ioh iol 1.8v 2.5v 3.3v 1.8v 2.5v 3.3v 1 1.9 2.7 3.1 2.1 2.8 3.3 2 3.4 4.4 4.9 2.9 3.8 4.4 3 5.4 7 7.9 4.9 6.5 7.4 4 6.8 8.6 9.6 5.7 7.3 8.2 5 8.6 11 12.4 7.6 9.9 11.2 6 9.9 12.5 14 8.3 10.7 12 7 11.8 14.8 16.6 10.2 13.2 14.9 8 11.6 14.6 16.3 10.2 13.2 14.9 9 12.91617.710.91415.7 10 14.7 18.2 20.2 12.7 16.3 18.3 11 15.9 19.5 21.6 13.4 17.1 19 12 17.4 21.6 23.9 15.1 19.2 21.3 13 19.2 23.7 26.2 16.3 20.9 23.5 14 21.5 26.3 28.9 18.2 23 25.6 15 22 27.1 29.8 18.7 23.9 26.8 n/a reserved
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 38 figure 23 and figure 24 illustrate quiescent current for ql1p 075 and ql1p100 with vlp = 0 v and 3.3 v. figure 23: quiescent current for ql1p075 and ql1p100 with vlp = 0 v figure 24: quiescent current for ql1p075 and ql1p100 with vlp = 3.3 v polarpro quiescent current 0 5 10 15 20 25 30 35 40 -40c 0c 25c 70c 85c 90c ambient temperature (c) current ( icc: vcc = 1.8v iccio: vccio = 3.6v iccm: ccmvcc = 1.8v polarpro quiescent current 0 20 40 60 80 100 120 140 -40c 0c 25c 70c 85c 90c ambient temperature (c) current ( icc: vcc = 1.8v iccio: vccio = 3.6v iccm: ccmvcc = 1.8v
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 39 figure 25 and figure 26 illustrate quiescent current for ql1p 200 and ql1p300 with vlp = 0 v and 3.3 v. figure 25: quiescent current for ql1p200 and ql1p300 with vlp = 0 v figure 26: quiescent current for ql1p200 and ql1p300 with vlp = 3.3 v polarpro quiescent current 0 50 100 150 200 250 300 350 -40c 0c 25c 70c 85c 90c 100c 125c temperature (c) static current ( a) icc: vcc = 1.8v iccio: vccio = 3.6v iccm: ccmvcc = 1.8v polarpro quiescent current 0 100 200 300 400 500 600 700 800 -40c 0c 25c 70c 85c 90c 100c 125c temperature (c) static current ( a) icc: vcc = 1.8v iccio: vccio = 3.6v iccm: ccmvcc = 1.8v
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 40 ac characteristics ac specifications are provided in table 35 through table 51 . logic cell diagrams and waveforms are provided in figure 27 through figure 42 . all of the following ac timing number s are for worst case commercial (t = 85c junction, v= 1.71v), and worst case industr ial (t = 100c junction, v=1.71v) conditions. figure 27: polarpro logic cell 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 d e q r s tz cz qz fz qds qst tbs tab tsl ti ta1 ta2 tb1 tb2 bab bsl bi ba1 ba2 bb1 bb2 fs f1 f2 qdi qen qck qrt
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 41 figure 28: logic cell flip-flop timings?first waveform table 35: logic cell delays symbol parameter commercial industrial min. max. min. max. t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output 0.32 ns 0.59 ns 0.34 ns 0.62 ns t su setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 0.23 ns 0.56 ns 0.24 ns 0.58 ns t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns 0.32 ns 0 ns 0.34 ns t esu enable setup time: time the enable input of the flip-flop must be stable before the active clock edge 0.23 ns 0.85 ns 0.89 ns 0.24 ns t ehl enable hold time: time the enable input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t co clock-to-out delay: the amount of time taken by the flip- flop to output after the active clock edge. 0.48 ns 0.52 ns 0.50 ns 0.55 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns 0.46 ns 0.46 ns 0.46 ns t cwlo clock low time: required minimum time that the clock stays low 0.46 ns 0.46 ns 0.46 ns 0.46 ns t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) 0.60 ns 0.60 ns 0.61 ns 0.61 ns t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) 0.68 ns 0.68 ns 0.71 ns 0.71 ns t sw set width: time that the set signal must remain high/low 0.30 ns 0.30 ns 0.30 ns 0.30 ns t rw reset width: time that the reset signal must remain high/low 0.30 ns 0.30 ns 0.30 ns 0.30 ns t reset t sw t rw t set clk qst (set) qrt (reset) q t cwhi (min) t cwlo (min)
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 42 figure 29: logic cell flip-flop timings?second waveform figure 30: polarpro clock network table 36: polarpro tree clock delay clock segment parameter commercial industrial min. max. min. max. t pgck delay from global clock pad input to quadrant network 1.54 ns 1.86 ns 1.56 ns 1.88 ns t pdck delay from dedicated clock pad input to quadrant network 1.4 ns 1.66 ns 1.42 ns 1.68 ns t bgck global clock tree delay (quad net to flip-flop) 20 ps 200 ps 30 ps 220 ps t gskew global delay clock skew 30 ps 190 ps 40 ps 200 ps t dskew dedicated clock skew 30 ps 190 ps 40 ps 200 ps t su t co clk d q t hl quadrant clock network global clock network x4 x4 x4 x4 x4 inversion mux quadrant clock network quadrant clock network quadrant clock network
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 43 ram timing figure 31: ram module a. x=8 for 4-kilobit ram blocks, x=9 for 8-kilobit ram blocks. table 37: ram cell synchronous write timing symbol parameter commercial industrial min. max. min. max. t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.29 ns 1.10 ns 0.31 ns 1.28 ns t hwa wa hold time to wclk: ti me the write address must be stable after the active edge of the write clock 0 ns 0.21 ns 0 ns 0.20 ns t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.31 ns 1.74 ns 0.40 ns 2.21 ns t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns 0.22 ns 0 ns 0.17 ns t sws wd_sel setup time to wc lk: time write chip select must be stable before the active edge of the write clock 0.42 ns 1.10 ns 0.49 ns 1.28 ns t hws wd_sel hold time to wclk : time write chip select must be stable after the acti ve edge of the write clock 0 ns 0.04 ns 0 ns 0.04 ns t swe wen setup time to wclk: time the write enable must be stable before the active edge of the write clock 0.63 ns 1.10 ns 0.74 ns 1.28 ns t hwe wen hold time to wclk: time the write enable must be stable after the active edge of the write clock 0 ns 0 ns 0 ns 0 ns rd[17:0] wd[17:0] wa[x:0] wen[1:0] wd_sel wclk ra[x:0] rd_sel rclk a a
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 44 figure 32: ram cell write timing table 38: ram cell synchronous read timing symbol parameter commercial industrial min. max. min. max. t sra ra setup time to rclk: time the read address must be stable before the active edge of the read clock 0.29 ns 1.10 ns 0.31 ns 1.28 ns t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns 0.21 ns 0 ns 0.20 ns t srs rd_sel setup time to rclk: time the read chip select must be stable before the active edge of the read clock 0.42 ns 1.10 ns 0.49 ns 1.28 ns t hrs rd_sel hold time to rclk: time the read chip select must be stable after the active edge of the read clock 0 ns 0.04 ns 0 ns 0.04 ns t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd 2.62 ns 5.67 ns 2.69 ns 5.88 ns t swa t hwa t swd t hwd t sws t hws wclk wa wd wd_sel t swe t hwe wen
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 45 figure 33: ram cell read timing fifo timing figure 34: fifo module t sra t hra t srs t hrs t rcrd rclk ra rd_sel rd new data old data din[x:0] push fifo_push_flush push_clk pop fifo_pop_flush pop_clk dout[x:0] almost_full almost_empty push_flag[3:0] pop_flag[3:0] a a a. x = {1,2,3,....35}.
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 46 figure 35: fifo push timing table 39: fifo push timing symbol parameter commercial industrial min. max. min. max. t spushd din setup time to push_clk: time din must be stable before the active edge of the fifo push clock 0.31 ns 1.74 ns 0.40 ns 2.21 ns t hpushd din hold time to push_clk: time din must be stable after the active edge of the fifo push clock 0 ns 0.22 ns 0 ns 0.17 ns t spushen push setup time to push_clk : time push must be stable before the active edge of the fifo push clock 1.07 ns 1.57 ns 1.38 ns 2.0 ns t hpushen push hold time to push_clk: time push must be stable after the active edge of the fifo push clock 0 ns 0 ns 0 ns 0 ns t spushflush flush setup time to push_clk: time fifo_push_flush must be stable before the active edge of the fifo push clock 1.11 ns 1.74 ns 1.43 ns 2.21 ns t hpushflush flush hold time to push_clk: time fifo_push_flush must be stable after the active edge of the fifo push clock 0 ns 0 ns 0 ns 0 ns t coaf clock-to-out of almost full 2.66 ns 3.34 ns 2.72 ns 3.42 ns t copushflag clock-to-out of fifo push level indicator 2.36 ns 4.20 ns 2.41 ns 4.32 ns push_clk din[x:0] push push_flag new status old status fifo_push_flush almost_full t spushd t hpushd t spushen t hpsuhen t hpush flush t spush flush t coaf t copushflag
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 47 figure 36: fifo pop timing table 40: fifo pop timing symbol parameter commercial industrial min. max. min. max. t spopen pop setup time to pop_clk: time pop must be stable before the active edge of the fifo pop clock 1.01 ns 1.13 ns 1.19 ns 1.32 ns t hpopen pop hold time to pop_clk: time pop must be stable after the active edge of the fifo pop clock 0 ns 0 ns 0 ns 0 ns t spopflush flush setup time to pop_clk: time fifo_pop_flush must be stable before the active edge of the fifo pop clock 1.11 ns 1.74 ns 1.43 ns 2.21 ns t hpopflush flush hold time to pop_clk: time fifo_pop_flush must be stable after the active edge of the fifo pop clock 0 ns 0 ns 0 ns 0 ns t fpop pop_clk to pop: clock-to-out from the active fifo clock edge and the time when the data is popped from the fifo at dout 2.32 ns 5.61 ns 2.37 ns 5.88 ns t coae clock-to-out of almost empty 2.64 ns 3.58 ns 2.70 ns 3.66 ns t copopflag clock-to-out of fifo pop level indi cator 2.32 ns 3.93 ns 2.38 ns 4.03 ns pop_clk dout[x:0] pop pop_flag new status old status fifo_pop_flush almost_empty t spopen t hpopen t spop flush t hpop flush t copop t coae t copopflag
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 48 gpio cell timing figure 37: polarpro i/o cell output path figure 38: polarpro i/o cell output enable timing fixhold logic dq d q dq outz outrz_en osel oez esel inz isel inrz_en fixhold rst clk di_en i/o pad enrz_en t outhl t outlh t pzl t pzh t plz t phz
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 49 table 44 lists the typical output slew rates (in v/ns) across th ree levels of output voltages, with a drive strength of 4, and a load capacitor of 10 pf. table 41: output timing characteristics @ vccio = 3.3 v, t = 25 c symbol parameter value (ns) slowest slew max. fastest slew max. t outlh output delay low to high (90% of h) 8.10 1.00 t outhl output delay high to low (10% of l) 9.60 0.90 t pzh output delay tri-state to high (90% of h) 3.40 0.30 t pzl output delay tri-state to low (10% of l) 3.90 0.30 t phz output delay high to tri-state 3.60 0.36 t plz output delay low to tri-state 4.1 0.41 table 42: output timing characteristics @ vccio = 2.5 v, t = 25 c symbol parameter value (ns) slowest slew max. fastest slew max. t outlh output delay low to high (90% of h) 12.20 1.10 t outhl output delay high to low (10% of l) 18.80 1.00 t pzh output delay tri-state to high (90% of h) 4.50 0.45 t pzl output delay tri-state to low (10% of l) 8.40 0.52 t phz output delay high to tri-state 8.10 0.52 t plz output delay low to tri-state 5.30 0.53 table 43: output timing characteristics @ vccio = 1.8 v, t = 25 c symbol parameter value (ns) slowest slew max. fastest slew max. t outlh output delay low to high (90% of h) 2.50 2.20 t outhl output delay high to low (10% of l) 1.70 1.40 t pzh output delay tri-state to high (90% of h) 8.30 0.70 t pzl output delay tri-state to low (10% of l) 24.70 1.05 t phz output delay high to tri-state 23.50 1.25 t plz output delay low to tri-state 10.80 0.78 table 44: gpio output slew rate slew output slew rate (v/ns) at vccio = 1.8 v 2.5 v 3.3 v slow n/a 0.20 0.36 fast n/a 0.31 0.66 vfast0.170.611.32 wow 0.25 1.18 2.03
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 50 table 45: i/o output register cell timing symbol parameter commercial industrial min. max. min. max. t osu output register setup time : time the synchronous outz input of the flip-f lop must be stable before the active clock edge 0.33 ns 0.38 ns 0.34 ns 0.36 ns t ohl output register hold time: time the synchronous outz input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oco output register clock-to-out: time taken by the flip-flop to output after the active clock edge 5.25 ns 5.99 ns 5.46 ns 6.29 ns t orst output register reset delay: time between when the flip- flop is ?reset? (low) and when the output is consequently ?reset? (low) 5.85 ns 5.85 ns 6.03 ns 6.03 ns t oesu output register clock enable setup time: time outrz_en must be stable before the active clock edge 0.33 ns 0.51 ns 0.30 ns 0.54 ns t oeh output register clock enable hold time: time outrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oezsu output register clock enable setup time: time oez must be stable before the active clock edge 0.14 ns 0.20 ns 0.15 ns 0.18 ns t oezh output register clock enable hold time: time oez must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t opd output signal propagation delay: propagation delay of outz to the output pad 4.82 ns 5.44 ns 5.03 ns 5.72 ns
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 51 figure 39: polarpro i/o cell input path figure 40: polarpro input register cell timing fixhold logic dq d q dq outz outrz_en osel oez esel inz isel inrz_en fixhold rst clk di_en i/o pad enrz_en clk rst d q e t irst t ieh t iesu t ico t ihl t isu
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 52 table 46: i/o in put register cell timing symbol parameter commercial industrial min. max. min. max. t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 2.51 ns 2.85 ns 2.80 ns 2.82 ns t ihl input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge 1.68 ns 2.66 ns 1.58 ns 2.70 ns t irst input register reset delay: time between when the flip- flop is ?reset? (low) and when the output is consequently ?reset? (low) 1.59 ns 1.59 ns 1.53 ns 1.53 ns t iesu input register clock enable setup time: time inrz_en must be stable before the active clock edge 0.25 ns 0.40 ns 0.23 ns 0.43 ns t ieh input register clock enable hold time: time inrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t idiensu input data enable setup time: time di_en must be stable before the active clock edge 2.39 ns 5.38 ns 2.28 ns 5.63 ns t idienh input data enable hold time: time di_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ifhsu input fixhold setup time: ti me fixhold must be stable before the active clock edge 2.39 ns 5.38 ns 2.28 ns 5.63 ns t ifhh input fixhold hold time: time fixhold must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns table 47: i/o input buffer delays symbol parameter value to get the total input delay add this delay to t isu min. max. t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications tbd tbd t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications tbd tbd t sid (lvcmos18) lvcmos18 input delay: low volta ge cmos for 1.8 v applications tbd tbd t sid (gtl+) gtl+ input delay: gunning transceiver logic tbd tbd t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v tbd tbd t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v tbd tbd t sid (pci) pci input delay: peripheral co mponent interconnect for 3.3 v tbd tbd
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 53 ddr cell timing figure 41: ddrio dq configuration table 48: dq cell timing symbol parameter commercial industrial min. max. min. max. t dqlsu output register setup time: ti me the synchronous dql input of the flip-flop must be stable before the active clock edge 0.37 ns 0.38 ns 0.35 ns 0.39 ns t dqlh output register hold time: time the synchronous dql input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oco output register clock-to-out: time taken by the dql flip-flop to output to the dq pad after the active clock edge 4.13 ns 4.39 ns 4.48 ns 4.85 ns t odqhsu output higher bit register clock setup time: time dqh must be stable before the active clock edge 0.32 ns 0.34 ns 0.31 ns 0.35 ns t odqhh output higher bit register clock hold time: time dqh must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t opd output propagation delay: propagation time from dql to the output pad 3.64 ns 3.92 ns 4.17 ns 4.20 ns dqs_shf clk_sync clk dqhi dqli/inz oez ddr_en clk 270 dqh dql/outz osel doi esel dq ddr_en ddr_en ddr_en vref + -
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 54 t idqsu input register setup time: time dq must be stable before the active clock edge 1.45 ns 1.48 ns 1.24 ns 1.69 ns t idqh input register hold time: time dq must be stable after the active clock edge 0.62 ns 0.65 ns 0.47 ns 0.83 ns t ipd input propagation delay: propagation time from dq to dqli 2.35 ns 2.63 ns 2.19 ns 2.75 ns table 49: dq cell configured as a gpio timing symbol parameter commercial industrial min. max. min. max. t osu output register setup time: time the synchronous outz input of the flip-flop must be stable before the active clock edge 0.37 ns 0.38 ns 0.35 ns 0.39 ns t oh output register hold time: time the synchronous outz input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oco output register clock-to-out: time taken by the outz flip-flop to output to the output pad after the active clock edge 4.17 ns 4.43 ns 4.61 ns 4.80 ns t oesu output data enable setup time: time oez must be stable before the active clock edge 0.43 ns 0.54 ns 0.42 ns 0.55 ns t oeh output data enable hold time: time oez must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oesu output register clock enable setup time: time outrz_en must be stable before the active clock edge 0.38 ns 0.64 ns 0.35 ns 0.67 ns t oeh output register clock enable hold time: time outrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t opd output propagation delay: propagation time from outz to the output pad 3.65 ns 3.87 ns 4.06 ns 4.24 ns t isu input register setup time: time the synchronous input of the flip- flop must be stable before the active clock edge 2.54 ns 2.63 ns 2.46 ns 2.62 ns t ihl input register hold time: time the synchronous input of the flip- flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ico input register clock-to-out: time taken by the flip-flop to output to inz after the active clock edge 2.88 ns 3.12 ns 2.73 ns 3.21 ns t iesu input register clock enable se tup time: time inrz_en must be stable before the active clock edge 0.26 ns 0.55 ns 0.23 ns 0.58 ns t ieh input register clock enable hold time: time inrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ipd input propagation delay: propagatio n time from the input pad to inz 2.35 ns 3.12 ns 2.19 ns 3.21 ns table 48: dq cell timing (continued) symbol parameter commercial industrial min. max. min. max.
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 55 figure 42: ddrio dqs configuration table 50: dqs cell timing symbol parameter commercial industrial min. max. min. max. t wesu output register setup time: time the synchronous wrt_en input of the flip-flop must be stable before the active clock edge 0.61 ns 0.64 ns 0.61 ns 0.64 ns t weh output register hold time: time the synchronous wrt_en input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t wepd output propagation delay: propagation time from wrt_en to the output pad 3.56 ns 3.62 ns 3.85 ns 3.99 ns t idqspd input propagation delay: propagation time from dqs to dqs_shf 1.58 ns 3.53 ns 1.37 ns 3.77 ns doi dqs vref + - dqs delay wrt_en/ outz clk osel resynch_wq_wr ddr_en oez isel inz dqs_shf fsel ddr_en resynch_ dq_wr
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 56 table 51: dqs cell configured as a gpio timing symbol parameter commercial industrial min. max. min. max. t osu output register setup time: time the synchronous outz input of the flip-flop must be stable before the active clock edge 0.47 ns 0.48 ns 0.45 ns 0.50 ns t oh output register hold time: time the synchronous outz input of the flip-flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oco output register clock-to-out: time taken by the outz flip-flop to output to the output pad af ter the active clock edge 4.14 ns 4.46 ns 4.66 ns 4.77ns t oesu output data enable setup time: time oez must be stable before the active clock edge 0.47 ns 0.49 ns 0.49 ns 0.49 ns t oeh output data enable hold time: time oez must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t oesu output register clock enable se tup time: time outrz_en must be stable before the active clock edge 0.35 ns 0.66 ns 0.33 ns 0.77 ns t oeh output register clock enable hold time: time outrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t opd output propagation delay: propagation time from outz to the output pad 3.88 ns 4.13 ns 4.41 ns 4.42 ns t isu input register setup time: time t he synchronous input of the flip- flop must be stable before the active clock edge 2.38 ns 2.45 ns 2.47 ns 2.29 ns t ihl input register hold ti me: time the synchronous input of the flip- flop must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ico input register clock-to-out: time taken by the flip-flop to output to inz after the active clock edge 2.76 ns 2.78 ns 2.73 ns 3.21 ns t iesu input register clock enable se tup time: time inrz_en must be stable before the active clock edge 0.40 ns 0.71 ns 0.23 ns 0.58 ns t ieh input register clock enable hold time: time inrz_en must be stable after the active clock edge 0 ns 0 ns 0 ns 0 ns t ipd input propagation delay: propagation time from the input pad to inz 2.25 ns 2.78 ns 2.19 ns 3.21 ns
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 57 package thermal characteristics the polarpro device is available for commercial (0c to 85c junction), industrial (-40c to 100c junction), and military (-55c to 125c junction) temperature ranges. thermal resistance equations: jc = (t j - t c )/p ja = (tj - ta)/p p max = (t jmax - t amax )/ ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 125c. to calculate the maximum power dissipation for a device package look up ja from table 52 , pick an appropriate t amax and use: p max = (125c - t amax ) / ja table 52: package thermal characteristics package description theta-ja ( c/w) device package code package type pin count 0 lfm 200 lfm 400 lfm ql1p075 pf tqfp 144 50 44 42 pt tfbga (12 mm x 12 mm) 196 42.0 35.0 33.5 ps lbga 256 48.2 41.7 40.2 ql1p100 pf tqfp 144 50 44 42 pt tfbga (12 mm x 12 mm) 196 42.0 35.0 33.5 ps lbga 256 48.2 41.7 40.2 ql1p150 ps lbga 256 35.5 29.0 27.7 ps lbga 324 tbd tbd tbd ql1p300 ps lbga 256 35.5 29.0 27.7 ps lbga 324 tbd tbd tbd ql1p600 ps lbga 256 tbd tbd tbd ps lbga 324 tbd tbd tbd ql1p1000 ps lbga 256 tbd tbd tbd ps lbga 324 tbd tbd tbd
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 58 moisture sensitivity level all polarpro devices are moisture sensitivity level 3. power vs. operating frequency the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where: lc = number of logic cells in the design ckbf = number of clock buffers clbf = number of column clock buffers ckld = number of loads connected to the column clock buffers ram = number of ram blocks pll = number of plls inp = number of input pins outp = number of output pins note: to learn more about power consumption, see quicklogic application note 60 at http://www.quicklogic.com/images/appnote60.pdf . table 53: solder and lead finish composition lead included lead-free bga solder 63% pb, 37% sn sn3agcu:sn4agcu a a. sn3agcu:sn4agcu means that ag can range from 3% to 4%. cu is always 0.5%. qfp lead finish 85% pb, 15% sn sn (matte)
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 59 power-up sequencing figure 43: power-up sequencing figure 43 shows an example where all vccio = 3.3 v. when powering up a polarpro device , vcc, vccio rails must take 10 s or longer to reach the maximum value (refer to figure 43 ). ramping vcc and vccio faster than 10 s can cause the device to behave improperly. it is also important to ensure vccio and vlp ar e within 500 mv of vcc when ramping up the power supplies. in the case where vccio or vlp are greater than vcc by more than 500 mv an additional current draw can occur as vcc passes its threshold voltage. in a case where vcc is greater than vccio by more than 500 mv the protection diodes between the power su pplies become forward biased . if this occurs then there will be an additional current load on the powe r supply. having the diodes on can cause a reliability problem, since it can wear out the diodes and subsequently damage the internal transistors. programming stipulation for polarpro devices to correctly program, there must not be any race conditions or internally generated free- running oscillators in the design. this will cause an icc programming failure during the programming process. quicklogic cannot guarantee the operation of any device that fails programming. therefore, race conditions and free-running oscillators must be removed from de signs so that polarpro devices can correctly pass programming. voltage v ccio ,vlp v cc |v ccio - v cc | max time 10 us v cc
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 60 pin descriptions table 54: pin descriptions pin direction function description dedicated pin descriptions gpio(c:a) i/o general purpose input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi -directional pin. the letter inside the parenthesis means that the i/o is located in the bank with that letter. if an i/ o is not used, the development software provides the option of tying that pin to gnd, vccio, or hi-z. clk(c:a) i global clock network pin low skew global clock this pin provides access to a distributed network capable of driving the cloc k, set, reset, all in puts to the logic cell, read and write clocks, read and write enables of the embedded ram blocks, and i/o inputs. the voltage tolerance of this pin is specified by vccio(c:a). dedclk(d) i dedicated clock network pin low skew clock this pin provides access to a distributed network capable of driving the cloc k, set, reset, all in puts to the logic cell, read and write clocks, read and write enables of the embedded ram blocks, and i/o inputs. the voltage tolerance of this pin is specified by vccio(d). ccmin(1:0) i ccm clock input input clock for ccm. the voltage tolerance for this pin is specified by the vccio of the same bank. ccmvcc (1:0) i power supply pin for ccm ccm input voltage level. configurable as 1.8 v only. ccmgnd(1:0) i ground pin for ccm connect to ground. vlp i voltage low power active low. therefore, when vlp pin is low, the device will go into low power mode. tie vlp to 3.3 v to disable low power mode. vcc i power supply pin connect to 1.8 v supply. vccio(d:a) i input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the letter inside the parenthesis means t hat the vccio is located in the bank with that letter. every i/o pin in the same bank will be tolerant of the same vcci o input signals and will drive vccio level output signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. gnd i ground pin connect to ground. dq/ gpio(d) i/o configurable pin can be declared as either a ddrio dq or as a general purpose i/o the d inside the parenthesis means that the i/o is located in bank d. if an i/o is not used, the development software provides the option of tying that pin to gnd, vccio, or hi- z. dqs/ gpio(d) i/o configurable pin can be declared as either a ddrio dqs or as a general purpose i/o the d inside the parenthesis means that the i/o is located in bank d. if an i/o is not used, the development software provides the option of tying that pin to gnd, vccio, or hi- z.
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 61 recommended unused pin terminations for polarpro devices all unused, general purpose i/o pins can be tied to vccio, gnd, or hi-z (high impedance) internally. by default, quicklogic quickworks so ftware ties unused i/os to gnd. terminate the rest of the pins at the board level as recommended in table 55 . dqck_n/ gpio(d) i/o configurable pin can be declared as either a ddrio dq, ddr negative clock, or as a general purpose i/o. the d inside the parenthesis means that the i/o is located in bank d. if an i/o is not used, the development software provides the option of tying that pin to gnd, vccio, or hi- z. dqck_p/ gpio(d) i/o configurable pin can be declared as either a ddrio dq, ddr positive clock, or as a general purpose i/o. the d inside the parenthesis means that the i/o is located in bank d. if an i/o is not used, the development software provides the option of typing th at pin to gnd, vccio, or hi-z. vref(d) i differential reference voltage the inref is the reference voltage pin for the sstl1.8 and sstl2 standards. the d inside the parenthesis means that inref is located in bank d. tie this pin to gnd if voltage referenced standards are not used. jtag pin descriptions tdi/rsi i test data in for jtag/ram init. serial data in hold high during normal operation. connect to vccio(b) if unused. trstb i active low reset for jtag hold low during normal operation. connect to gnd if unused. during jtag, a high voltage is based on vccio(b). tms i test mode select for jtag hold high during normal operation. connect to vccio(b) if not used for jtag. tck i test clock for jtag hold high or low during normal operation. connect to vccio(b) or gnd if not used for jtag. tdo o test data out for jtag must be left unconnected if not used for jtag. the output voltage drive is specified by vccio(b). table 55: recommended unused pin terminations signal name recommended termination vref if an i/o bank does not require the use of the inref signal, connect the pin to gnd. clk a a. x represents a, b, c or d. connect to gnd or vccio(x) if unused. vlp tie vlp to 3.3 v to disable low power mode. ccmvcc(1:0) if a ccm is not used, the corresponding ccmvcc may be tied to gnd to reduce power consumption. if a ccm is used, do not try to disable the ccm by tying the ccmvcc to gnd. tdi connect to vccio(b) if not used for jtag. trstb connect to gnd if not used for jtag. tms connect to vccio(b) if not used for jtag tck connect to vccio(b) or gnd if not used for jtag. tdo must be left unconnected if not used for jtag. table 54: pin descriptions (continued) pin direction function description
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 62 packaging pinout tables polarpro ql1p075 - 132 tfbga pinout table table 56: ql1p075 ? 132 tfbga pinout table pin function pin function pin function pin function a1 vcc d7 dq/gpio(d) h1 clk(c) l9 gpio(b) a2 vccio(d) d8 dq/gpio(d) h3 tck l10 gpio(b) a3 dqs/gpio(d) d9 dq/gpio(d) h4 gpio(c) l11 gpio(a) a4 dqck_p/gpio(d) d10 dq/gpio(d) h6 gnd l12 gpio(a) a5 dqck_n/gpio(d) d11 gpio(a) h7 gnd l14 gpio(a) a6 dq/gpio(d) d12 gpio(a) h8 gnd m1 vcc a7 dedclk(d) d14 vccio(a) h9 gnd m3 gpio(b) a8 dq/gpio(d) e1 vccio(c) h11 gpio(a) m4 gpio(b) a9 dqs/gpio(d) e3 gpio(c) h12 gpio(a) m5 gpio(b) a10 dqck_p/gpio(d) e4 dq/gpio(d) h14 vcc m6 gpio(b) a11 dqck_n/gpio(d) e11 gpio(a) j1 gpio(c) m7 gpio(b) a12 vccio(d) e12 gpio(a) j3 gpio(c) m8 vcc a13 gnd e14 gpio(a) j4 gpio(c) m9 gpio(b) a14 vcc f1 vcc j6 gpio(c) m10 gpio(b) b1 vref f3 gpio(c) j7 gpio(b) m11 gpio(b) b14 ccmgnd(1) f4 gnd j8 gnd m12 gpio(a) c1 gpio(c) f6 tms j9 gpio(a) m14 vccio(a) c3 gpio(c) f7 gnd j11 gpio(a) n1 gnd c4 dq/gpio(d) f8 gnd j12 gpio(a) n14 vcc c5 dq/gpio(d) f9 gpio(a) j14 clk(a)/ccmin(1) p1 vccio(b) c6 vcc f11 gpio(a) k1 vccio(c) p2 gpio(b) c7 dq/gpio(d) f12 gpio(a) k3 gpio(c) p3 tdo c8 vccio(d) f14 vccio(a) k4 vccio(b) p4 gpio(b) c9 dq/gpio(d) g1 vcc k11 gpio(a) p5 vccio(b) c10 dq/gpio(d) g3 gpio(c) k12 trstb p6 gpio(b) c11 vref g4 gpio(c) k14 vccio(b) p7 clk(b) c12 ccmvcc(1) g6 gnd l1 gpio(c) p8 clk(b) c14 gpio(a) g7 gnd l3 gpio(c) p9 vcc d1 gpio(c) g8 gnd l4 gpio(c) p10 vccio(b) d3 gpio(c) g9 gnd l5 gpio(c) p11 gpio(b) d4 vccio(d) g11 gpio(a) l6 gpio(c) p12 gpio(b) d5 dq/gpio(d) g12 gpio(a) l7 gpio(b) p13 vlp d6 dq/gpio(d) g14 vcc l8 tdi p14 gnd
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 63 polarpro ql1p075 - 144 tqfp pinout table table 57: ql1p075 ? 144 tqfp pinout table pin function pin function pin function pin function 1 vccio(c) 37 gnd 73 vccio(a) 109 vccio(d) 2 gpio(c) 38 gpio(b) 74 gpio(a) 110 vref(d) 3 gpio(c) 39 gpio(b) 75 gpio(a) 111 dq/gpio(d) 4 gpio(c) 40 tdo 76 gpio(a) 112 dq/gpio(d) 5 gpio(c) 41 vccio(b) 77 gpio(a) 113 dq/gpio(d) 6 gpio(c) 42 gpio(b) 78 gpio(a) 114 dq/gpio(d) 7 gpio(c) 43 gpio(b) 79 vccio(b) 115 dqck_p/gpio(d) 8 gpio(c) 44 gpio(b) 80 gpio(a) 116 dqck_n/gpio(d) 9 gpio(c) 45 gpio(b) 81 trstb 117 dqs/gpio(d) 10 gpio(c) 46 gpio(b) 82 gpio(a) 118 dq/gpio(d) 11 gpio(c) 47 gpio(b) 83 gpio(a) 119 dq/gpio(d) 12 gpio(c) 48 gpio(b) 84 clk(a)/ccmin(1) 120 dq/gpio(d) 13 vcc 49 gpio(b) 85 gpio(a) 121 tms 14 gpio(c) 50 gpio(b) 86 vccio(a) 122 dq/gpio(d) 15 gpio(c) 51 gpio(b) 87 gpio(a) 123 dq/gpio(d) 16 vcc 52 tdi 88 gpio(a) 124 vcc 17 gpio(c) 53 clk(b) 89 gpio(a) 125 dedclk(d) 18 gpio(c) 54 vccio(b) 90 vcc 126 vccio(d) 19 vccio(c) 55 vcc 91 gpio(a) 127 dq/gpio(d) 20 gpio(c) 56 clk(b) 92 gpio(a) 128 dq/gpio(d) 21 gpio(c) 57 gpio(b) 93 vcc 129 dq/gpio(d) 22 gpio(c) 58 vcc 94 gpio(a) 130 dq/gpio(d) 23 clk(c) 59 gpio(b) 95 gpio(a) 131 dqck_n/gpio(d) 24 tck 60 gpio(b) 96 gpio(a) 132 dqck_p/gpio(d) 25 gpio(c) 61 gpio(b) 97 gpio(a) 133 dqs/gpio(d) 26 gpio(c) 62 gpio(b) 98 gpio(a) 134 dq/gpio(d) 27 vccio(b) 63 gpio(b) 99 gpio(a) 135 dq/gpio(d) 28 gpio(c) 64 gpio(b) 100 gpio(a) 136 dq/gpio(d) 29 gpio(c) 65 gpio(b) 101 gpio(a) 137 dq/gpio(d) 30 gpio(c) 66 gpio(b) 102 gpio(a) 138 vref(d) 31 gpio(c) 67 gpio(b) 103 gpio(a) 139 dq/gpio(d) 32 gpio(c) 68 gpio(b) 104 ccmvcc(1) 140 vccio(d) 33 gpio(c) 69 vccio(b) 105 vccio(a) 141 vcc 34 vccio(c) 70 vlp 106 ccmgnd(1) 142 vccio(d) 35 gnd 71 gnd 107 gnd 143 gnd 36 gnd 72 gnd 108 gnd 144 gnd
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 64 polarpro ql1p075 - 196 tfbga (1 2 mm x 12 mm) pinout table table 58: ql1p075 ? 196 tfbga (12 mm x 12 mm) pinout table pin function pin function pin function pin function pin function a1 dqs/gpio(d) c13 dq/gpio(d) f11 gpio(a) j9 gnd m7 gpio(b) a2 dqck_p/gpio(d) c14 dq/gpio(d) f12 gpio(a) j10 vcc m8 gpio(b) a3 dqck_n/gpio(d) d1 gpio(c) f13 gpio(a) j11 vccio(b) m9 gpio(b) a4 dq/gpio(d) d2 gnd f14 gpio(a) j12 gpio(a) m10 gpio(b) a5 dq/gpio(d) d3 dq/gpio(d) g1 gpio(c) j13 gpio(a) m11 gpio(b) a6 dqck_p/gpio(d) d4 dq/gpio(d) g2 gpio(c) j14 gpio(a) m12 gpio(a) a7 dqck_n/gpio(d) d5 dq/gpio(d) g3 gpio(c) k1 gpio(c) m13 gpio(a) a8 dq/gpio(d) d6 dq/gpio(d) g4 tck k2 gpio(c) m14 gpio(a) a9 dqck_p/gpio(d) d7 dq/gpio(d) g5 vcc k3 gpio(c) n1 gpio(c) a10 dqck_n/gpio(d) d8 dq/gpio(d) g6 gnd k4 gnd n2 gpio(c) a11 dq/gpio(d) d9 dq/gpio(d) g7 gnd k5 vccio(b) n3 gpio(b) a12 dq/gpio(d) d10 dq/gpio(d) g8 gnd k6 vccio(b) n4 gpio(b) a13 dqck_p/gpio(d) d11 dqs/gpio(d) g9 gnd k7 vcc n5 gpio(b) a14 dqck_n/gpio(d) d12 dq/gpio(d) g10 vcc k8 vccio(b) n6 gpio(b) b1 dq/gpio(d) d13 dq/gpio(d) g11 gpio(a) k9 vccio(b) n7 clk(b) b2 dq/gpio(d) d14 gnd g12 gpio(a) k10 vccio(a) n8 gpio(b) b3 dq/gpio(d) e1 gpio(c) g13 gpio(a) k11 gpio(a) n9 gpio(b) b4 vref(d) e2 gpio(c) g14 gpio(a) k12 gpio(a) n10 gpio(b) b5 dq/gpio(d) e3 gpio(c) h1 clk(c)/ccmin(0) k13 gpio(a) n11 gpio(b) b6 dq/gpio(d) e4 ccmgnd(0) h2 gpio(c) k14 gpio(a) n12 gpio(b) b7 dedclk(d) e5 vccio(c) h3 gpio(c) l1 gpio(c) n13 vlp b8 tms e6 vccio(d) h4 vccio(b) l2 gpio(c) n14 gpio(a) b9 vref(d) e7 vccio(d) h5 vcc l3 gpio(c) p1 gpio(c) b10 dq/gpio(d) e8 vcc h6 gnd l4 gpio(b) p2 gpio(b) b11 dq/gpio(d) e9 vccio(d) h7 gnd l5 gpio(b) p3 gpio(b) b12 dqs/gpio(d) e10 vccio(d) h8 gnd l6 gpio(b) p4 gpio(b) b13 dq/gpio(d) e11 ccmgnd(1) h9 gnd l7 tdo p5 gpio(b) b14 dq/gpio(d) e12 ccmvcc(1) h10 vcc l8 tdi p6 clk(b) c1 gpio(c) e13 gpio(a) h11 gpio(a) l9 gpio(b) p7 gpio(b) c2 dq/gpio(d) e14 gpio(a) h12 gpio(a) l10 gnd p8 gpio(b) c3 dq/gpio(d) f1 gpio(c) h13 gpio(a) l11 gpio(a) p9 gpio(b) c4 dq/gpio(d) f2 gpio(c) h14 clk(a)/ccmin(1) l12 gpio(a) p10 gpio(b) c5 dq/gpio(d) f3 gpio(c) j1 gpio(c) l13 gpio(a) p11 gpio(b) c6 dqs/gpio(d) f4 ccmvcc(0) j2 gpio(c) l14 trstb p12 gpio(b) c7 dq/gpio(d) f5 vcc j3 gpio(c) m1 gpio(c) p13 gpio(a) c8 dq/gpio(d) f6 gnd j4 gnd m2 gpio(c) p14 gpio(a) c9 dq/gpio(d) f7 gnd j5 vccio(c) m3 gpio(c) c10 dq/gpio(d) f8 gnd j6 gnd m4 gpio(b) c11 dq/gpio(d) f9 gnd j7 gnd m5 gpio(b) c12 dq/gpio(d) f10 vccio(a) j8 gnd m6 gpio(b)
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 65 polarpro ql1p075 - 256 lbga pinout table table 59: ql1p075 ? 256 lbga pinout table pin function pin function pin function pin function pin function pin function a1 gnd c12 dqck_p/gpio(d) f7 vcc j2 gpio(c) l13 nc p8 gpio(b) a2 dq/gpio(d) c13 dqck_n/gpio(d) f8 gnd j3 gpio(c) l14 gpio(a) p9 gpio(b) a3 dq/gpio(d) c14 gnd f9 tms j4 gpio(c) l15 gpio(a) p10 gpio(b) a4 dq/gpio(d) c15 dq/gpio(d) f10 vcc j5 vccio(c) l16 gpio(a) p11 gpio(b) a5 dq/gpio(d) c16 dq/gpio(d) f11 dq/gpio(d) j6 gnd m1 nc p12 gpio(b) a6 dq/gpio(d) d1 gpio(c) f12 ccmvcc(1) j7 gnd m2 nc p13 gpio(b) a7 dqs/gpio(d) d2 nc f13 gpio(a) j8 vcc m3 gpio(b) p14 gnd a8 dq/gpio(d) d3 nc f14 gpio(a) j9 vcc m4 gpio(b) p15 gpio(b) a9 dedclk(d) d4 nc f15 gpio(a) j10 gnd m5 gpio(b) p16 gpio(b) a10 dq/gpio(d) d5 vref(d) f16 gpio(a) j11 trstb m6 vccio(b) r1 gpio(b) a11 dq/gpio(d) d6 dqs/gpio(d) g1 gpio(c) j12 vccio(a) m7 vccio(b) r2 gpio(b) a12 dq/gpio(d) d7 dq/gpio(d) g2 gpio(c) j13 gpio(a) m8 vccio(b) r3 gpio(b) a13 dq/gpio(d) d8 dq/gpio(d) g3 gpio(c) j14 gpio(a) m9 vccio(b) r4 gpio(b) a14 dq/gpio(d) d9 dqs/gpio(d) g4 gpio(c) j15 gpio(a) m10 vccio(b) r5 tdo a15 nc d10 dqck_p/gpio(d) g5 gpio(c) j16 clk(a)/ccmin(1) m11 vccio(b) r6 gpio(b) a16 gnd d11 dq/gpio(d) g6 vcc k1 gpio(c) m12 gpio(b) r7 gpio(b) b1 dq/gpio(d) d12 vref(d) g7 gnd k2 gpio(c) m13 nc r8 gpio(b) b2 dq/gpio(d) d13 dq/gpio(d) g8 gnd k3 gpio(c) m14 gpio(a) r9 gpio(b) b3 dq/gpio(d) d14 nc g9 gnd k4 gpio(c) m15 gpio(a) r10 gpio(b) b4 dq/gpio(d) d15 nc g10 gnd k5 gpio(c) m16 nc r11 gpio(b) b5 dq/gpio(d) d16 nc g11 vcc k6 vcc n1 gpio(b) r12 gpio(b) b6 dq/gpio(d) e1 gpio(c) g12 gpio(a) k7 gnd n2 gpio(b) r13 gpio(b) b7 dqck_p/gpio(d) e2 gpio(c) g13 gpio(a) k8 gnd n3 gpio(b) r14 gpio(b) b8 dqck_n/gpio(d) e3 gpio(c) g14 gpio(a) k9 gnd n4 gpio(b) r15 gpio(b) b9 dq/gpio(d) e4 gpio(c) g15 gpio(a) k10 gnd n5 gpio(b) r16 gpio(b) b10 dq/gpio(d) e5 ccmgnd(0) g16 gpio(a) k11 vcc n6 gpio(b) t1 gnd b11 dq/gpio(d) e6 vccio(d) h1 clk(c)/ccmin(0) k12 gpio(a) n7 gpio(b) t2 gpio(b) b12 dq/gpio(d) e7 vccio(d) h2 gpio(c) k13 gpio(a) n8 gpio(b) t3 gpio(b) b13 dq/gpio(d) e8 vccio(d) h3 gpio(c) k14 gpio(a) n9 gpio(b) t4 gpio(b) b14 dq/gpio(d) e9 vccio(d) h4 gpio(c) k15 gpio(a) n10 gpio(b) t5 gpio(b) b15 dq/gpio(d) e10 vccio(d) h5 vccio(c) k16 gpio(a) n11 gpio(b) t6 gpio(b) b16 dqs/gpio(d) e11 vccio(d) h6 tck l1 gpio(c) n12 gpio(b) t7 clk(b) c1 nc e12 ccmgnd(1) h7 gnd l2 gpio(c) n13 gpio(b) t8 gpio(b) c2 gpio(c) e13 gpio(a) h8 vcc l3 gpio(c) n14 gpio(b) t9 clk(b) c3 gnd e14 gpio(a) h9 vcc l4 nc n15 nc t10 gpio(b) c4 dq/gpio(d) e15 gpio(a) h10 gnd l5 nc n16 gpio(b) t11 gpio(b) c5 dqck_p/gpio(d) e16 gpio(a) h11 gnd l6 gnd p1 gpio(b) t12 gpio(b) c6 dqck_n/gpio(d) f1 gpio(c) h12 vccio(a) l7 vcc p2 gpio(b) t13 gpio(b) c7 dq/gpio(d) f2 gpio(c) h13 gpio(a) l8 tdi p3 gnd t14 gpio(b) c8 dq/gpio(d) f3 gpio(c) h14 gpio(a) l9 gnd p4 gpio(b) t15 gpio(b) c9 dq/gpio(d) f4 gpio(c) h15 gpio(a) l10 vcc p5 gpio(b) t16 gnd c10 dqck_n/gpio(d) f5 ccmvcc(0) h16 gpio(a) l11 vccio(b) p6 gpio(b) c11 dq/gpio(d) f6 vccio(b) j1 gpio(c) l12 vlp p7 gpio(b)
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 66 polarpro ql1p100 - 132 tfbga pinout table table 60: ql1p100 ? 132 tfbga pinout table pin function pin function pin function pin function a1 vcc d7 dq/gpio(d) h1 clk(c) l9 gpio(b) a2 vccio(d) d8 dq/gpio(d) h3 tck l10 gpio(b) a3 dqs/gpio(d) d9 dq/gpio(d) h4 gpio(c) l11 gpio(a) a4 dqck_p/gpio(d) d10 dq/gpio(d) h6 gnd l12 gpio(a) a5 dqck_n/gpio(d) d11 gpio(a) h7 gnd l14 gpio(a) a6 dq/gpio(d) d12 gpio(a) h8 gnd m1 vcc a7 dedclk(d) d14 vccio(a) h9 gnd m3 gpio(b a8 dq/gpio(d) e1 vccio(c) h11 gpio(a) m4 gpio(b) a9 dqs/gpio(d) e3 gpio(c) h12 gpio(a) m5 gpio(b) a10 dqck_p/gpio(d) e4 dq/gpio(d) h14 vcc m6 gpio(b) a11 dqck_n/gpio(d) e11 gpio(a) j1 gpio(c) m7 gpio(b) a12 vccio(d) e12 gpio(a) j3 gpio(c) m8 vcc a13 gnd e14 gpio(a) j4 gpio(c) m9 gpio(b) a14 vcc f1 vcc j6 gpio(c) m10 gpio(b) b1 vref f3 gpio(c) j7 gpio(b) m11 gpio(b) b14 ccmgnd(1) f4 gnd j8 gnd m12 gpio(a) c1 gpio(c) f6 tms j9 gpio(a) m14 vccio(a) c3 gpio(c) f7 gnd j11 gpio(a) n1 gnd c4 dq/gpio(d) f8 gnd j12 gpio(a) n14 vcc c5 dq/gpio(d) f9 gpio(a) j14 clk(a)/ccmin(1) p1 vccio(b) c6 vcc f11 gpio(a) k1 vccio(c) p2 gpio(b) c7 dq/gpio(d) f12 gpio(a) k3 gpio(c) p3 tdo c8 vccio(d) f14 vccio(a) k4 vccio(b) p4 gpio(b) c9 dq/gpio(d) g1 vcc k11 gpio(a) p5 vccio(b) c10 dq/gpio(d) g3 gpio(c) k12 trstb p6 gpio(b) c11 vref g4 gpio(c) k14 vccio(b) p7 clk(b) c12 ccmvcc(1) g6 gnd l1 gpio(c) p8 clk(b) c14 gpio(a) g7 gnd l3 gpio(c) p9 vcc d1 gpio(c) g8 gnd l4 gpio(c) p10 vccio(b) d3 gpio(c) g9 gnd l5 gpio(c) p11 gpio(b) d4 vccio(d) g11 gpio(a) l6 gpio(c) p12 gpio(b) d5 dq/gpio(d) g12 gpio(a) l7 gpio(b) p13 vlp d6 dq/gpio(d) g14 vcc l8 tdi p14 gnd
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 67 polarpro ql1p100 - 144 tqfp pinout table table 61: ql1p100 ? 144 tqfp pinout table pin function pin function pin function pin function 1 vccio(c) 37 gnd 73 vccio(a) 109 vccio(d) 2 gpio(c) 38 gpio(b) 74 gpio(a) 110 vref(d) 3 gpio(c) 39 gpio(b) 75 gpio(a) 111 dq/gpio(d) 4 gpio(c) 40 tdo 76 gpio(a) 112 dq/gpio(d) 5 gpio(c) 41 vccio(b) 77 gpio(a) 113 dq/gpio(d) 6 gpio(c) 42 gpio(b) 78 gpio(a) 114 dq/gpio(d) 7 gpio(c) 43 gpio(b) 79 vccio(b) 115 dqck_p/gpio(d) 8 gpio(c) 44 gpio(b) 80 gpio(a) 116 dqck_n/gpio(d) 9 gpio(c) 45 gpio(b) 81 trstb 117 dqs/gpio(d) 10 gpio(c) 46 gpio(b) 82 gpio(a) 118 dq/gpio(d) 11 gpio(c) 47 gpio(b) 83 gpio(a) 119 dq/gpio(d) 12 gpio(c) 48 gpio(b) 84 clk(a)/ccmin(1) 120 dq/gpio(d) 13 vcc 49 gpio(b) 85 gpio(a) 121 tms 14 gpio(c) 50 gpio(b) 86 vccio(a) 122 dq/gpio(d) 15 gpio(c) 51 gpio(b) 87 gpio(a) 123 dq/gpio(d) 16 vcc 52 tdi 88 gpio(a) 124 vcc 17 gpio(c) 53 clk(b) 89 gpio(a) 125 dedclk(d) 18 gpio(c) 54 vccio(b) 90 vcc 126 vccio(d) 19 vccio(c) 55 vcc 91 gpio(a) 127 dq/gpio(d) 20 gpio(c) 56 clk(b) 92 gpio(a) 128 dq/gpio(d) 21 gpio(c) 57 gpio(b) 93 vcc 129 dq/gpio(d) 22 gpio(c) 58 vcc 94 gpio(a) 130 dq/gpio(d) 23 clk(c) 59 gpio(b) 95 gpio(a) 131 dqck_n/gpio(d) 24 tck 60 gpio(b) 96 gpio(a) 132 dqck_p/gpio(d) 25 gpio(c) 61 gpio(b) 97 gpio(a) 133 dqs/gpio(d) 26 gpio(c) 62 gpio(b) 98 gpio(a) 134 dq/gpio(d) 27 vccio(b) 63 gpio(b) 99 gpio(a) 135 dq/gpio(d) 28 gpio(c) 64 gpio(b) 100 gpio(a) 136 dq/gpio(d) 29 gpio(c) 65 gpio(b) 101 gpio(a) 137 dq/gpio(d) 30 gpio(c) 66 gpio(b) 102 gpio(a) 138 vref(d) 31 gpio(c) 67 gpio(b) 103 gpio(a) 139 dq/gpio(d) 32 gpio(c) 68 gpio(b) 104 ccmvcc(1) 140 vccio(d) 33 gpio(c) 69 vccio(b) 105 vccio(a) 141 vcc 34 vccio(c) 70 vlp 106 ccmgnd(1) 142 vccio(d) 35 gnd 71 gnd 107 gnd 143 gnd 36 gnd 72 gnd 108 gnd 144 gnd
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 68 polarpro ql1p100 - 196 tfbga (1 2 mm x 12 mm) pinout table table 62: ql1p100 ? 196 tfbga (12 mm x 12 mm) pinout table pin function pin function pin function pin function pin function a1 dqs/gpio(d) c13 dq/gpio(d) f11 gpio(a) j9 gnd m7 gpio(b) a2 dqck_p/gpio(d) c14 dq/gpio(d) f12 gpio(a) j10 vcc m8 gpio(b) a3 dqck_n/gpio(d) d1 gpio(c) f13 gpio(a) j11 vccio(b) m9 gpio(b) a4 dq/gpio(d) d2 gnd f14 gpio(a) j12 gpio(a) m10 gpio(b) a5 dq/gpio(d) d3 dq/gpio(d) g1 gpio(c) j13 gpio(a) m11 gpio(b) a6 dqck_p/gpio(d) d4 dq/gpio(d) g2 gpio(c) j14 gpio(a) m12 gpio(a) a7 dqck_n/gpio(d) d5 dq/gpio(d) g3 gpio(c) k1 gpio(c) m13 gpio(a) a8 dq/gpio(d) d6 dq/gpio(d) g4 tck k2 gpio(c) m14 gpio(a) a9 dqck_p/gpio(d) d7 dq/gpio(d) g5 vcc k3 gpio(c) n1 gpio(c) a10 dqck_n/gpio(d) d8 dq/gpio(d) g6 gnd k4 gnd n2 gpio(c) a11 dq/gpio(d) d9 dq/gpio(d) g7 gnd k5 vccio(b) n3 gpio(b) a12 dq/gpio(d) d10 dq/gpio(d) g8 gnd k6 vccio(b) n4 gpio(b) a13 dqck_p/gpio(d) d11 dqs/gpio(d) g9 gnd k7 vcc n5 gpio(b) a14 dqck_n/gpio(d) d12 dq/gpio(d) g10 vcc k8 vccio(b) n6 gpio(b) b1 dq/gpio(d) d13 dq/gpio(d) g11 gpio(a) k9 vccio(b) n7 clk(b) b2 dq/gpio(d) d14 gnd g12 gpio(a) k10 vccio(a) n8 gpio(b) b3 dq/gpio(d) e1 gpio(c) g13 gpio(a) k11 gpio(a) n9 gpio(b) b4 vref(d) e2 gpio(c) g14 gpio(a) k12 gpio(a) n10 gpio(b) b5 dq/gpio(d) e3 gpio(c) h1 clk(c)/ccmin(0) k13 gpio(a) n11 gpio(b) b6 dq/gpio(d) e4 ccmgnd(0) h2 gpio(c) k14 gpio(a) n12 gpio(b) b7 dedclk(d) e5 vccio(c) h3 gpio(c) l1 gpio(c) n13 vlp b8 tms e6 vccio(d) h4 vccio(b) l2 gpio(c) n14 gpio(a) b9 vref(d) e7 vccio(d) h5 vcc l3 gpio(c) p1 gpio(c) b10 dq/gpio(d) e8 vcc h6 gnd l4 gpio(b) p2 gpio(b) b11 dq/gpio(d) e9 vccio(d) h7 gnd l5 gpio(b) p3 gpio(b) b12 dqs/gpio(d) e10 vccio(d) h8 gnd l6 gpio(b) p4 gpio(b) b13 dq/gpio(d) e11 ccmgnd(1) h9 gnd l7 tdo p5 gpio(b) b14 dq/gpio(d) e12 ccmvcc(1) h10 vcc l8 tdi p6 clk(b) c1 gpio(c) e13 gpio(a) h11 gpio(a) l9 gpio(b) p7 gpio(b) c2 dq/gpio(d) e14 gpio(a) h12 gpio(a) l10 gnd p8 gpio(b) c3 dq/gpio(d) f1 gpio(c) h13 gpio(a) l11 gpio(a) p9 gpio(b) c4 dq/gpio(d) f2 gpio(c) h14 clk(a)/ccmin(1) l12 gpio(a) p10 gpio(b) c5 dq/gpio(d) f3 gpio(c) j1 gpio(c) l13 gpio(a) p11 gpio(b) c6 dqs/gpio(d) f4 ccmvcc(0) j2 gpio(c) l14 trstb p12 gpio(b) c7 dq/gpio(d) f5 vcc j3 gpio(c) m1 gpio(c) p13 gpio(a) c8 dq/gpio(d) f6 gnd j4 gnd m2 gpio(c) p14 gpio(a) c9 dq/gpio(d) f7 gnd j5 vccio(c) m3 gpio(c) c10 dq/gpio(d) f8 gnd j6 gnd m4 gpio(b) c11 dq/gpio(d) f9 gnd j7 gnd m5 gpio(b) c12 dq/gpio(d) f10 vccio(a) j8 gnd m6 gpio(b)
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 69 polarpro ql1p100 - 256 lbga pinout table table 63: ql1p100 ? 256 lbga pinout table pin function pin function pin function pin function pin function pin function a1 gnd c12 dqck_p/gpio(d) f7 vcc j2 gpio(c) l13 gpio(a) p8 gpio(b) a2 dq/gpio(d) c13 dqck_n/gpio(d) f8 gnd j3 gpio(c) l14 gpio(a) p9 gpio(b) a3 dq/gpio(d) c14 gnd f9 tms j4 gpio(c) l15 gpio(a) p10 gpio(b) a4 dq/gpio(d) c15 dq/gpio(d) f10 vcc j5 vccio(c) l16 gpio(a) p11 gpio(b) a5 dq/gpio(d) c16 dq/gpio(d) f11 dq/gpio(d) j6 gnd m1 gpio(c) p12 gpio(b) a6 dq/gpio(d) d1 gpio(c) f12 ccmvcc(1) j7 gnd m2 gpio(c) p13 gpio(b) a7 dqs/gpio(d) d2 gpio(c) f13 gpio(a) j8 vcc m3 gpio(b) p14 gnd a8 dq/gpio(d) d3 gpio(c) f14 gpio(a) j9 vcc m4 gpio(b) p15 gpio(b) a9 dedclk(d) d4 gpio(c) f15 gpio(a) j10 gnd m5 gpio(b) p16 gpio(b) a10 dq/gpio(d) d5 vref(d) f16 gpio(a) j11 trstb m6 vccio(b) r1 gpio(b) a11 dq/gpio(d) d6 dqs/gpio(d) g1 gpio(c) j12 vccio(a) m7 vccio(b) r2 gpio(b) a12 dq/gpio(d) d7 dq/gpio(d) g2 gpio(c) j13 gpio(a) m8 vccio(b) r3 gpio(b) a13 dq/gpio(d) d8 dq/gpio(d) g3 gpio(c) j14 gpio(a) m9 vccio(b) r4 gpio(b) a14 dq/gpio(d) d9 dqs/gpio(d) g4 gpio(c) j15 gpio(a) m10 vccio(b) r5 tdo a15 gpio(a) d10 dqck_p/gpio(d) g5 gpio(c) j16 clk(a) ccmin(1) m11 vccio(b) r6 gpio(b) a16 gnd d11 dq/gpio(d) g6 vcc k1 gpio(c) m12 gpio(b) r7 gpio(b) b1 dq/gpio(d) d12 vref(d) g7 gnd k2 gpio(c) m13 gpio(a) r8 gpio(b) b2 dq/gpio(d) d13 dq/gpio(d) g8 gnd k3 gpio(c) m14 gpio(a) r9 gpio(b) b3 dq/gpio(d) d14 gpio(a) g9 gnd k4 gpio(c) m15 gpio(a) r10 gpio(b) b4 dq/gpio(d) d15 gpio(a) g10 gnd k5 gpio(c) m16 gpio(a) r11 gpio(b) b5 dq/gpio(d) d16 gpio(a) g11 vcc k6 vcc n1 gpio(b) r12 gpio(b) b6 dq/gpio(d) e1 gpio(c) g12 gpio(a) k7 gnd n2 gpio(b) r13 gpio(b) b7 dqck_p/gpio(d) e2 gpio(c) g13 gpio(a) k8 gnd n3 gpio(b) r14 gpio(b) b8 dqck_n/gpio(d) e3 gpio(c) g14 gpio(a) k9 gnd n4 gpio(b) r15 gpio(b) b9 dq/gpio(d) e4 gpio(c) g15 gpio(a) k10 gnd n5 gpio(b) r16 gpio(b) b10 dq/gpio(d) e5 ccmgnd(0) g16 gpio(a) k11 vcc n6 gpio(b) t1 gnd b11 dq/gpio(d) e6 vccio(d) h1 clk(c)/ ccmin(0) k12 gpio(a) n7 gpio(b) t2 gpio(b) b12 dq/gpio(d) e7 vccio(d) h2 gpio(c) k13 gpio(a) n8 gpio(b) t3 gpio(b) b13 dq/gpio(d) e8 vccio(d) h3 gpio(c) k14 gpio(a) n9 gpio(b) t4 gpio(b) b14 dq/gpio(d) e9 vccio(d) h4 gpio(c) k15 gpio(a) n10 gpio(b) t5 gpio(b) b15 dq/gpio(d) e10 vccio(d) h5 vccio(c) k16 gpio(a) n11 gpio(b) t6 gpio(b) b16 dqs/gpio(d) e11 vccio(d) h6 tck l1 gpio(c) n12 gpio(b) t7 clk(b) c1 gpio(c) e12 ccmgnd(1) h7 gnd l2 gpio(c) n13 gpio(b) t8 gpio(b) c2 gpio(c) e13 gpio(a) h8 vcc l3 gpio(c) n14 gpio(b) t9 clk(b) c3 gnd e14 gpio(a) h9 vcc l4 gpio(c) n15 gpio(a) t10 gpio(b) c4 dq/gpio(d) e15 gpio(a) h10 gnd l5 gpio(c) n16 gpio(b) t11 gpio(b) c5 dqck_p/gpio(d) e16 gpio(a) h11 gnd l6 gnd p1 gpio(b) t12 gpio(b) c6 dqck_n/gpio(d) f1 gpio(c) h12 vccio(a) l7 vcc p2 gpio(b) t13 gpio(b) c7 dq/gpio(d) f2 gpio(c) h13 gpio(a) l8 tdi p3 gnd t14 gpio(b) c8 dq/gpio(d) f3 gpio(c) h14 gpio(a) l9 gnd p4 gpio(b) t15 gpio(b) c9 dq/gpio(d) f4 gpio(c) h15 gpio(a) l10 vcc p5 gpio(b) t16 gnd c10 dqck_n/gpio(d) f5 ccmvcc(0) h16 gpio(a) l11 vccio(b) p6 gpio(b) c11 dq/gpio(d) f6 vccio(b) j1 gpio(c) l12 vlp p7 gpio(b)
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 70 polarpro ql1p200 - 132 tfbga pinout table table 64: polarpro ql1p200 ? 132 tfbga pin function pin function pin function pin function a1 vcc d7 dq/gpio(d) h1 clk(c)/ccmin(0) l9 gpio(b) a2 vcc d8 dq/gpio(d) h3 vccio(c) l10 gpio(b) a3 vref d9 dq/gpio(d) h4 gpio(c) l11 gpio(a) a4 dqs/gpio(d) d10 vccio(d) h6 gnd l12 gpio(a) a5 dqck_p/gpio(d) d11 gpio(a) h7 gnd l14 gpio(a) a6 dqck_n/gpio(d) d12 vccio(a) h8 gnd m1 vcc a7 dedclk(d) d14 gpio(a) h9 gnd m3 gnd a8 vccio(d) e1 vccio(c) h11 gpio(a) m4 gpio(b) a9 dqs/gpio(d) e3 gpio(c) h12 gpio(a) m5 gpio(b) a10 dqck_n/gpio(d) e4 gpio(c) h14 clk(a)/ccmin(1) m6 gpio(b) a11 dqck_p/gpio(d) e11 gpio(a) j1 gpio(c) m7 gpio(b) a12 dq/gpio(d) e12 gpio(a) j3 tck m8 gpio(b) a13 vref e14 vccio(a) j4 vccio(b) m9 gpio(b) a14 vcc f1 gpio(c) j6 gpio(c) m10 vccio(b) b1 ccmvcc(0) f3 gpio(c) j7 tdi m11 gpio(b) b14 ccmvcc(1) f4 gpio(c) j8 gnd m12 gpio(a) c1 ccmgnd(0) f6 vccio(d) j9 gpio(a) m14 vccio(a) c3 gnd f7 tms j11 gpio(a) n1 gnd c4 dq/gpio(d) f8 gnd j12 vccio(a) n14 vlp c5 vcc f9 dq/gpio(d) j14 vccio(b) p1 vcc c6 dq/gpio(d) f11 gpio(a) k1 vccio(c) p2 tdo c7 dq/gpio(d) f12 gpio(a) k3 gpio(c) p3 gpio(b) c8 dq/gpio(d) f14 gpio(a) k4 gpio(c) p4 vccio(b) c9 dq/gpio(d) g1 gpio(c) k11 trstb p5 gpio(b) c10 dq/gpio(d) g3 gpio(c) k12 gpio(a) p6 clk(b) c11 gnd g4 gpio(c) k14 gpio(a) p7 clk(b) c12 ccmgnd(1) g6 gnd l1 vcc p8 vccio(b) c14 vcc g7 gnd l3 gpio(c) p9 gpio(b) d1 gpio(c) g8 gnd l4 gpio(c) p10 vcc d3 gpio(c) g9 gnd l5 gpio(b) p11 vcc d4 dq/gpio(d) g11 gpio(a) l6 gpio(b) p12 gpio(a) d5 dq/gpio(d) g12 gpio(a) l7 gpio(b) p13 gnd d6 dq/gpio(d) g14 gpio(a) l8 gpio(b) p14 vcc
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 71 polarpro ql1p200 - 256 lbga pinout table table 65: polarpro ql1p200 - 256 lbga pin function pin function pin function pin function pin function pin function a1 gnd c12 dqck_n/gpio(d) f7 vcc j2 gpio(c) l13 gpio(a) p8 gpio(b) a2 dq/gpio(d) c13 dqck_p/gpio(d) f8 gnd j3 gpio(c) l14 gpio(a) p9 gpio(b) a3 dq/gpio(d) c14 gnd f9 tms j4 gpio(c) l15 gpio(a) p10 gpio(b) a4 dq/gpio(d) c15 dq/gpio(d) f10 vcc j5 vccio(c) l16 gpio(a) p11 gpio(b) a5 dq/gpio(d) c16 dq/gpio(d) f11 dq/gpio(d) j6 gnd m1 gpio(c) p12 gpio(b) a6 dq/gpio(d) d1 gpio(c) f12 ccmvcc(1) j7 gnd m2 gpio(c) p13 gpio(b) a7 dqs/gpio(d) d2 gpio(c) f13 gpio(a) j8 vcc m3 gpio(b) p14 gnd a8 dq/gpio(d) d3 gpio(c) f14 gpio(a) j9 vcc m4 gpio(b) p15 gpio(b) a9 dedclk(d) d4 gpio(c) f15 gpio(a) j10 gnd m5 gpio(b) p16 gpio(b) a10 dq/gpio(d) d5 vref(d) f16 gpio(a) j11 trstb m6 vccio(b) r1 gpio(b) a11 dq/gpio(d) d6 dqs/gpio(d) g1 gpio(c) j12 vccio(a) m7 vccio(b) r2 gpio(b) a12 dq/gpio(d) d7 dq/gpio(d) g2 gpio(c) j13 gpio(a) m8 vccio(b) r3 gpio(b) a13 dq/gpio(d) d8 dq/gpio(d) g3 gpio(c) j14 gpio(a) m9 vccio(b) r4 gpio(b) a14 dq/gpio(d) d9 dqs/gpio(d) g4 gpio(c) j15 gpio(a) m10 vccio(b) r5 tdo a15 gpio(a) d10 dqck_p/gpio(d) g5 gpio(c) j16 clk(a)/ccmin(1) m11 vccio(b) r6 gpio(b) a16 gnd d11 dq/gpio(d) g6 vcc k1 gpio(c) m12 gpio(b) r7 gpio(b) b1 dq/gpio(d) d12 vref(d) g7 gnd k2 gpio(c) m13 gpio(a) r8 gpio(b) b2 dq/gpio(d) d13 dq/gpio(d) g8 gnd k3 gpio(c) m14 gpio(a) r9 gpio(b) b3 dq/gpio(d) d14 gpio(a) g9 gnd k4 gpio(c) m15 gpio(a) r10 gpio(b) b4 dq/gpio(d) d15 gpio(a) g10 gnd k5 gpio(c) m16 gpio(a) r11 gpio(b) b5 dq/gpio(d) d16 gpio(a) g11 vcc k6 vcc n1 gpio(b) r12 gpio(b) b6 dq/gpio(d) e1 gpio(c) g12 gpio(a) k7 gnd n2 gpio(b) r13 gpio(b) b7 dqck_n/gpio(d) e2 gpio(c) g13 gpio(a) k8 gnd n3 gpio(b) r14 gpio(b) b8 dqck_p/gpio(d) e3 gpio(c) g14 gpio(a) k9 gnd n4 gpio(b) r15 gpio(b) b9 dq/gpio(d) e4 gpio(c) g15 gpio(a) k10 gnd n5 gpio(b) r16 gpio(b) b10 dq/gpio(d) e5 ccmgnd(0) g16 gpio(a) k11 vcc n6 gpio(b) t1 gnd b11 dq/gpio(d) e6 vccio(d) h1 clk(c)/ccmin(0) k12 gpio(a) n7 gpio(b) t2 gpio(b) b12 dq/gpio(d) e7 vccio(d) h2 gpio(c) k13 gpio(a) n8 gpio(b) t3 gpio(b) b13 dq/gpio(d) e8 vccio(d) h3 gpio(c) k14 gpio(a) n9 gpio(b) t4 gpio(b) b14 dq/gpio(d) e9 vccio(d) h4 gpio(c) k15 gpio(a) n10 gpio(b) t5 gpio(b) b15 dq/gpio(d) e10 vccio(d) h5 vccio(c) k16 gpio(a) n11 gpio(b) t6 gpio(b) b16 dqs/gpio(d) e11 vccio(d) h6 tck l1 gpio(c) n12 gpio(b) t7 clk(b) c1 gpio(c) e12 ccmgnd(1) h7 gnd l2 gpio(c) n13 gpio(b) t8 gpio(b) c2 gpio(c) e13 gpio(a) h8 vcc l3 gpio(c) n14 gpio(b) t9 clk(b) c3 gnd e14 gpio(a) h9 vcc l4 gpio(c) n15 gpio(a) t10 gpio(b) c4 dq/gpio(d) e15 gpio(a) h10 gnd l5 gpio(c) n16 gpio(b) t11 gpio(b) c5 dqck_n/gpio(d) e16 gpio(a) h11 gnd l6 gnd p1 gpio(b) t12 gpio(b) c6 dqck_p/gpio(d) f1 gpio(c) h12 vccio(a) l7 vcc p2 gpio(b) t13 gpio(b) c7 dq/gpio(d) f2 gpio(c) h13 gpio(a) l8 tdi p3 gnd t14 gpio(b) c8 dq/gpio(d) f3 gpio(c) h14 gpio(a) l9 gnd p4 gpio(b) t15 gpio(b) c9 dq/gpio(d) f4 gpio(c) h15 gpio(a) l10 vcc p5 gpio(b) t16 gnd c10 dqck_n/gpio(d) f5 ccmvcc(0) h16 gpio(a) l11 vccio(b) p6 gpio(b) c11 dq/gpio(d) f6 vccio(b) j1 gpio(c) l12 vlp p7 gpio(b)
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 72 polarpro ql1p300 - 132 tfbga pinout table table 66: polarpro ql1p300 - 132 tfbga pin function pin function pin function pin function a1 vcc d7 dq/gpio(d) h1 clk(c)/ccmin(0) l9 gpio(b) a2 vcc d8 dq/gpio(d) h3 vccio(c) l10 gpio(b) a3 vref d9 dq/gpio(d) h4 gpio(c) l11 gpio(a) a4 dqs/gpio(d) d10 vccio(d) h6 gnd l12 gpio(a) a5 dqck_p/gpio(d) d11 gpio(a) h7 gnd l14 gpio(a) a6 dqck_n/gpio(d) d12 vccio(a) h8 gnd m1 vcc a7 dedclk(d) d14 gpio(a) h9 gnd m3 gnd a8 vccio(d) e1 vccio(c) h11 gpio(a) m4 gpio(b) a9 dqs/gpio(d) e3 gpio(c) h12 gpio(a) m5 gpio(b) a10 dqck_n/gpio(d) e4 gpio(c) h14 clk(a)/ccmin(1) m6 gpio(b) a11 dqck_p/gpio(d) e11 gpio(a) j1 gpio(c) m7 gpio(b) a12 dq/gpio(d) e12 gpio(a) j3 tck m8 gpio(b) a13 vref e14 vccio(a) j4 vccio(b) m9 gpio(b) a14 vcc f1 gpio(c) j6 gpio(c) m10 vccio(b) b1 ccmvcc(0) f3 gpio(c) j7 tdi m11 gpio(b) b14 ccmvcc(1) f4 gpio(c) j8 gnd m12 gpio(a) c1 ccmgnd(0) f6 vccio(d) j9 gpio(a) m14 vccio(a) c3 gnd f7 tms j11 gpio(a) n1 gnd c4 dq/gpio(d) f8 gnd j12 vccio(a) n14 vlp c5 vcc f9 dq/gpio(d) j14 vccio(b) p1 vcc c6 dq/gpio(d) f11 gpio(a) k1 vccio(c) p2 tdo c7 dq/gpio(d) f12 gpio(a) k3 gpio(c) p3 gpio(b) c8 dq/gpio(d) f14 gpio(a) k4 gpio(c) p4 vccio(b) c9 dq/gpio(d) g1 gpio(c) k11 trstb p5 gpio(b) c10 dq/gpio(d) g3 gpio(c) k12 gpio(a) p6 clk(b) c11 gnd g4 gpio(c) k14 gpio(a) p7 clk(b) c12 ccmgnd(1) g6 gnd l1 vcc p8 vccio(b) c14 vcc g7 gnd l3 gpio(c) p9 gpio(b) d1 gpio(c) g8 gnd l4 gpio(c) p10 vcc d3 gpio(c) g9 gnd l5 gpio(b) p11 vcc d4 dq/gpio(d) g11 gpio(a) l6 gpio(b) p12 gpio(a) d5 dq/gpio(d) g12 gpio(a) l7 gpio(b) p13 gnd d6 dq/gpio(d) g14 gpio(a) l8 gpio(b) p14 vcc
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 73 polarpro ql1p300 - 256 lbga pinout table table 67: ql1p300 ? 256 lbga pinout table pin function pin function pin function pin function pin function pin function a1 gnd c12 dqck_p/gpio(d) f7 vcc j2 gpio(c) l13 gpio(a) p8 gpio(b) a2 dq/gpio(d) c13 dqck_n/gpio(d) f8 gnd j3 gpio(c) l14 gpio(a) p9 gpio(b) a3 dq/gpio(d) c14 gnd f9 tms j4 gpio(c) l15 gpio(a) p10 gpio(b) a4 dq/gpio(d) c15 dq/gpio(d) f10 vcc j5 vccio(c) l16 gpio(a) p11 gpio(b) a5 dq/gpio(d) c16 dq/gpio(d) f11 dq/gpio(d) j6 gnd m1 gpio(c) p12 gpio(b) a6 dq/gpio(d) d1 gpio(c) f12 ccmvcc(1) j7 gnd m2 gpio(c) p13 gpio(b) a7 dqs/gpio(d) d2 gpio(c) f13 gpio(a) j8 vcc m3 gpio(b) p14 gnd a8 dq/gpio(d) d3 gpio(c) f14 gpio(a) j9 vcc m4 gpio(b) p15 gpio(b) a9 dedclk(d) d4 gpio(c) f15 gpio(a) j10 gnd m5 gpio(b) p16 gpio(b) a10 dq/gpio(d) d5 vref(d) f16 gpio(a) j11 trstb m6 vccio(b) r1 gpio(b) a11 dq/gpio(d) d6 dqs/gpio(d) g1 gpio(c) j12 vccio(a) m7 vccio(b) r2 gpio(b) a12 dq/gpio(d) d7 dq/gpio(d) g2 gpio(c) j13 gpio(a) m8 vccio(b) r3 gpio(b) a13 dq/gpio(d) d8 dq/gpio(d) g3 gpio(c) j14 gpio(a) m9 vccio(b) r4 gpio(b) a14 dq/gpio(d) d9 dqs/gpio(d) g4 gpio(c) j15 gpio(a) m10 vccio(b) r5 tdo a15 gpio(a) d10 dqck_p/gpio(d) g5 gpio(c) j16 clk(a) ccmin(1) m11 vccio(b) r6 gpio(b) a16 gnd d11 dq/gpio(d) g6 vcc k1 gpio(c) m12 gpio(b) r7 gpio(b) b1 dq/gpio(d) d12 vref(d) g7 gnd k2 gpio(c) m13 gpio(a) r8 gpio(b) b2 dq/gpio(d) d13 dq/gpio(d) g8 gnd k3 gpio(c) m14 gpio(a) r9 gpio(b) b3 dq/gpio(d) d14 gpio(a) g9 gnd k4 gpio(c) m15 gpio(a) r10 gpio(b) b4 dq/gpio(d) d15 gpio(a) g10 gnd k5 gpio(c) m16 gpio(a) r11 gpio(b) b5 dq/gpio(d) d16 gpio(a) g11 vcc k6 vcc n1 gpio(b) r12 gpio(b) b6 dq/gpio(d) e1 gpio(c) g12 gpio(a) k7 gnd n2 gpio(b) r13 gpio(b) b7 dqck_p/gpio(d) e2 gpio(c) g13 gpio(a) k8 gnd n3 gpio(b) r14 gpio(b) b8 dqck_n/gpio(d) e3 gpio(c) g14 gpio(a) k9 gnd n4 gpio(b) r15 gpio(b) b9 dq/gpio(d) e4 gpio(c) g15 gpio(a) k10 gnd n5 gpio(b) r16 gpio(b) b10 dq/gpio(d) e5 ccmgnd(0) g16 gpio(a) k11 vcc n6 gpio(b) t1 gnd b11 dq/gpio(d) e6 vccio(d) h1 clk(c)/ ccmin(0) k12 gpio(a) n7 gpio(b) t2 gpio(b) b12 dq/gpio(d) e7 vccio(d) h2 gpio(c) k13 gpio(a) n8 gpio(b) t3 gpio(b) b13 dq/gpio(d) e8 vccio(d) h3 gpio(c) k14 gpio(a) n9 gpio(b) t4 gpio(b) b14 dq/gpio(d) e9 vccio(d) h4 gpio(c) k15 gpio(a) n10 gpio(b) t5 gpio(b) b15 dq/gpio(d) e10 vccio(d) h5 vccio(c) k16 gpio(a) n11 gpio(b) t6 gpio(b) b16 dqs/gpio(d) e11 vccio(d) h6 tck l1 gpio(c) n12 gpio(b) t7 clk(b) c1 gpio(c) e12 ccmgnd(1) h7 gnd l2 gpio(c) n13 gpio(b) t8 gpio(b) c2 gpio(c) e13 gpio(a) h8 vcc l3 gpio(c) n14 gpio(b) t9 clk(b) c3 gnd e14 gpio(a) h9 vcc l4 gpio(c) n15 gpio(a) t10 gpio(b) c4 dq/gpio(d) e15 gpio(a) h10 gnd l5 gpio(c) n16 gpio(b) t11 gpio(b) c5 dqck_p/gpio(d) e16 gpio(a) h11 gnd l6 gnd p1 gpio(b) t12 gpio(b) c6 dqck_n/gpio(d) f1 gpio(c) h12 vccio(a) l7 vcc p2 gpio(b) t13 gpio(b) c7 dq/gpio(d) f2 gpio(c) h13 gpio(a) l8 tdi p3 gnd t14 gpio(b) c8 dq/gpio(d) f3 gpio(c) h14 gpio(a) l9 gnd p4 gpio(b) t15 gpio(b) c9 dq/gpio(d) f4 gpio(c) h15 gpio(a) l10 vcc p5 gpio(b) t16 gnd c10 dqck_n/gpio(d) f5 ccmvcc(0) h16 gpio(a) l11 vccio(b) p6 gpio(b) c11 dq/gpio(d) f6 vccio(b) j1 gpio(c) l12 vlp p7 gpio(b)
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 74 packaging pinout diagrams polarpro ql1pxxx - 132 tfbga (8 mm x 8 mm) pinout diagram top bottom
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 75 polarpro ql1pxxx - 144 tqfp pinout diagram pin 1 pin 37 pin 73 pin 109 ql1pxxx-7pf144c polarpro
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 76 polarpro ql1pxxx - 196 tfbga (1 2 mm x 12 mm) pinout diagram top bottom
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 77 polarpro ql1pxxx - 256 lbga pinout diagram top bottom
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 78 package mechanical drawings 132 tfbga packaging drawing
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 79 144 tqfp packaging drawing
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 80 144 tqfp packaging drawing (continued)
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 81 196 tfbga (12 mm x 12 mm) package drawing
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 82 256 lbga package drawing
? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 83 packaging information the polarpro product family packaging in formation is presented in table 68 . ordering information * lead-free packaging is denoted by the character 'n' pr eceding the number of pins. for availability, contact quicklogic (see contact information). table 68: packaging options device information device ql1p075 / ql1p100 ql1p200 / ql1p300 ql1p600 / ql1p1000 pin pitch pin pitch pin pitch package definitions a a. tfbga = thin profile fi ne pitch ball grid array lbga = low profile ball grid array tqfp = thin quad flat pack 132 tfbga (8 mm x 8mm) 0.50 mm 132 tfbga (8 mm x 8mm) 0.50 mm 256 lbga 1.0 mm 144 tqfp 0.50 mm 256 lbga 1.0 mm 324 lbga 1.0 mm 196 tfbga (12 mm x 12 mm) 0.80 mm 256 lbga 1.0 mm ql 1p075 -6 pf144 c operating range: c = commercial i = industrial m = military package lead count: pu132 (pun132)* = 132-pin tfbga (0.5mm) pf144 (pfn144)* = 144-pin tqfp (0.5mm) pt196 (ptn196)* = 196-pin tfbga (0.8mm) ps256 (psn256)* = 256-pin lbga (1.0mm) ps324 (psn324)* = 324-pin lbga (1.0mm) speed grade: -6 - fast -7 - faster -8 - fastest part number: 1p075 1p100 1p150 1p300 1p600 1p1000 quicklogic device
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? quicklogic polarpro? data sheet rev. g 84 contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history copyright and trademark information copyright ? 2006 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic and the quicklogic logo, and quickworks are registered trademarks of quicklogic corporation; polarpro and spde are trademarks of quicklogic corporation. revision date originator and comments a november 2005 jason lew and kathleen murchek first release b march 2005 jason lew and kathleen murchek c march 2005 jason lew and kathleen murchek d june 2006 senani gunaratna and kathleen murchek e august 2006 jason lew and kathleen murchek f august 2006 jason lew and kathleen murchek g september 2006 jason lew and kathleen murchek

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